Datasheet> 器件分类 > 存储> 存储> MT42L96M64D3LD-3IT:A

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MT42L96M64D3LD-3IT:A: 产品描述DDR DRAM, 96MX64, CMOS, PBGA220, 14 X 14 MM, GREEN, FBGA-220; 产品类别存储存储; 文件大小2MB，共164页; 制造商Micron Technology; 官网地址http://www.mdtic.com.tw/

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MT42L96M64D3LD-3IT:A概述

DDR DRAM, 96MX64, CMOS, PBGA220, 14 X 14 MM, GREEN, FBGA-220

MT42L96M64D3LD-3IT:A规格参数

参数名称	属性值
厂商名称	Micron Technology
包装说明	VFBGA,
Reach Compliance Code	compliant
访问模式	MULTI BANK PAGE BURST
其他特性	SELF REFRESH; IT ALSO REQUIRES 1.2V NOM
JESD-30 代码	S-PBGA-B220
长度	14 mm
内存密度	6442450944 bit
内存集成电路类型	DDR DRAM
内存宽度	64
功能数量	1
端口数量	1
端子数量	220
字数	100663296 words
字数代码	96000000
工作模式	SYNCHRONOUS
组织	96MX64
封装主体材料	PLASTIC/EPOXY
封装代码	VFBGA
封装形状	SQUARE
封装形式	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
座面最大高度	1 mm
自我刷新	YES
最大供电电压 (Vsup)	1.95 V
最小供电电压 (Vsup)	1.7 V
标称供电电压 (Vsup)	1.8 V
表面贴装	YES
技术	CMOS
端子形式	BALL
端子节距	0.5 mm
端子位置	BOTTOM
宽度	14 mm
Base Number Matches	1

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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4

Features

Mobile LPDDR2 SDRAM

MT42L128M16D1, MT42L64M32D1, MT42L64M64D2,

MT42L128M32D2, MT42L256M32D4, MT42L128M64D4

MT42L96M64D3, MT42L192M32D3

Features

• Ultra low-voltage core and I/O power supplies

– V

DD2

= 1.14–1.30V

– V

DDCA

DDQ

= 1.14–1.30V

– V

DD1

= 1.70–1.95V

• Clock frequency range

– 533–10 MHz (data rate range: 1066–20 Mb/s/pin)

• Four-bit prefetch DDR architecture

• Eight internal banks for concurrent operation

• Multiplexed, double data rate, command/address

inputs; commands entered on every CK edge

• Bidirectional/differential data strobe per byte of

data (DQS/DQS#)

• Programmable READ and WRITE latencies (RL/WL)

• Programmable burst lengths: 4, 8, or 16

• Per-bank refresh for concurrent operation

• On-chip temperature sensor to control self refresh

rate

• Partial-array self refresh (PASR)

• Deep power-down mode (DPD)

• Selectable output drive strength (DS)

• Clock stop capability

• RoHS-compliant, “green” packaging

Table 1: Key Timing Parameters

Speed

Grade

-18

-25

-3

Clock

Rate

(MHz)

533

400

333

Data Rate

(Mb/s/pin) RL WL

1066

800

667

Options

• V

DD2

: 1.2V

• Configuration

– 16 Meg x 16 x 8 banks x 1 die

– 8 Meg x 32 x 8 banks x 1 die

– 8 Meg x 32 x 8 banks x 2 die

– 16 Meg x 16 x 8 banks x 4 die

– 8 Meg x 32 x 8 banks x 2 die

– 8 Meg x 32 x 8 banks x 3 die

– 8 Meg x 32 x 8 banks x 4 die

– 16 Meg x 16 x 8 banks x 2 die +

8 Meg x 32 x 8 banks x 1 die

• Device type

– LPDDR2-S4, 1 die in package

– LPDDR2-S4, 2 die in package

– LPDDR2-S4, 3 die in package

– LPDDR2-S4, 4 die in package

• FBGA“green” package

– 134-ball FBGA (11mm x 11.5mm)

– 134-ball FBGA (11.5mm x 11.5mm)

– 168-ball FBGA (12mm x 12mm)

– 216-ball FBGA (12mm x 12mm)

– 220-ball FBGA (14mm x 14mm)

• Timing – cycle time

– 1.875ns @ RL = 8

– 2.5ns @ RL = 6

– 3.0ns @ RL = 5

• Operating temperature range

– From –25°C to +85°C

– From –40°C to +105°C

• Revision

Notes:

Marking

128M16

64M32

128M32

256M32

64M64

96M64

128M64

192M32

-18

-25

-3

RCD/

Typical

1. For fast

RCD/

RP, contact factory.

2. For -18 speed grade, contact factory.

PDF: 09005aef83f3f2eb

2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

2Gb: x16, x32 Mobile LPDDR2 SDRAM S4

Features

Contents

General Description ....................................................................................................................................... 11

General Notes ............................................................................................................................................ 11

Specifications ........................................................................................................................................... 12

Package Block Diagrams ................................................................................................................................. 16

Package Dimensions ....................................................................................................................................... 23

Ball Assignments and Descriptions ................................................................................................................. 33

Functional Description ................................................................................................................................... 39

Power-Up ....................................................................................................................................................... 40

Initialization After RESET (Without Voltage Ramp) ...................................................................................... 42

Power-Off ....................................................................................................................................................... 42

Uncontrolled Power-Off .............................................................................................................................. 43

Mode Register Definition ................................................................................................................................ 43

Mode Register Assignments and Definitions ................................................................................................ 43

ACTIVATE Command ..................................................................................................................................... 54

8-Bank Device Operation ............................................................................................................................ 54

Read and Write Access Modes ......................................................................................................................... 55

Burst READ Command ................................................................................................................................... 55

READs Interrupted by a READ ..................................................................................................................... 62

Burst WRITE Command .................................................................................................................................. 62

WRITEs Interrupted by a WRITE ................................................................................................................. 65

BURST TERMINATE Command ...................................................................................................................... 65

Write Data Mask ............................................................................................................................................. 67

PRECHARGE Command ................................................................................................................................. 68

READ Burst Followed by PRECHARGE ......................................................................................................... 69

WRITE Burst Followed by PRECHARGE ....................................................................................................... 70

Auto Precharge ........................................................................................................................................... 71

READ Burst with Auto Precharge ................................................................................................................. 71

WRITE Burst with Auto Precharge ............................................................................................................... 72

REFRESH Command ...................................................................................................................................... 74

REFRESH Requirements ............................................................................................................................. 80

SELF REFRESH Operation ............................................................................................................................... 82

Partial-Array Self Refresh – Bank Masking .................................................................................................... 83

Partial-Array Self Refresh – Segment Masking .............................................................................................. 84

MODE REGISTER READ ................................................................................................................................. 85

Temperature Sensor ................................................................................................................................... 87

DQ Calibration ........................................................................................................................................... 89

MODE REGISTER WRITE Command ............................................................................................................... 91

MRW RESET Command .............................................................................................................................. 91

MRW ZQ Calibration Commands ................................................................................................................ 92

ZQ External Resistor Value, Tolerance, and Capacitive Loading ..................................................................... 94

Power-Down .................................................................................................................................................. 94

Deep Power-Down ........................................................................................................................................ 101

Input Clock Frequency Changes and Stop Events ............................................................................................ 102

Input Clock Frequency Changes and Clock Stop with CKE LOW .................................................................. 102

Input Clock Frequency Changes and Clock Stop with CKE HIGH ................................................................. 103

NO OPERATION Command ........................................................................................................................... 103

Simplified Bus Interface State Diagram ....................................................................................................... 103

Truth Tables .................................................................................................................................................. 105

Electrical Specifications ................................................................................................................................. 113

Absolute Maximum Ratings ....................................................................................................................... 113

PDF: 09005aef83f3f2eb

2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

2Gb: x16, x32 Mobile LPDDR2 SDRAM S4

Features

Input/Output Capacitance ......................................................................................................................... 113

Electrical Specifications – I

Specifications and Conditions ........................................................................... 114

AC and DC Operating Conditions ................................................................................................................... 117

AC and DC Logic Input Measurement Levels for Single-Ended Signals ............................................................. 119

REF

Tolerances ......................................................................................................................................... 120

Input Signal .............................................................................................................................................. 121

AC and DC Logic Input Measurement Levels for Differential Signals ................................................................ 123

Single-Ended Requirements for Differential Signals .................................................................................... 124

Differential Input Crosspoint Voltage ......................................................................................................... 126

Input Slew Rate ......................................................................................................................................... 127

Output Characteristics and Operating Conditions ........................................................................................... 127

Single-Ended Output Slew Rate .................................................................................................................. 128

Differential Output Slew Rate ..................................................................................................................... 129

HSUL_12 Driver Output Timing Reference Load ......................................................................................... 131

Output Driver Impedance .............................................................................................................................. 131

Output Driver Impedance Characteristics with ZQ Calibration .................................................................... 132

Output Driver Temperature and Voltage Sensitivity ..................................................................................... 133

Output Impedance Characteristics Without ZQ Calibration ......................................................................... 133

Clock Specification ........................................................................................................................................ 137

CK(abs),

CH(abs), and

CL(abs) ................................................................................................................ 138

Clock Period Jitter .......................................................................................................................................... 138

Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 138

Cycle Time Derating for Core Timing Parameters ........................................................................................ 139

Clock Cycle Derating for Core Timing Parameters ....................................................................................... 139

Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 139

Clock Jitter Effects on READ Timing Parameters .......................................................................................... 139

Clock Jitter Effects on WRITE Timing Parameters ........................................................................................ 140

Refresh Requirements .................................................................................................................................... 141

AC Timing ..................................................................................................................................................... 142

CA and CS# Setup, Hold, and Derating ........................................................................................................... 149

Data Setup, Hold, and Slew Rate Derating ....................................................................................................... 156

Revision History ............................................................................................................................................ 163

Rev. N, Production – 3/12 ........................................................................................................................... 163

Rev. M, Production – 10/11 ........................................................................................................................ 163

Rev. L, Production – 09/11 .......................................................................................................................... 163

Rev. K, Production – 08/11 ......................................................................................................................... 163

Rev. J, Production – 05/11 .......................................................................................................................... 163

Rev. H, Production – 3/11 ........................................................................................................................... 163

Rev. G, Production – 1/11 ........................................................................................................................... 163

Rev. F, Advance – 11/10 .............................................................................................................................. 163

Rev. E, Advance – 09/10 .............................................................................................................................. 163

Rev. D, Advance – 07/10 ............................................................................................................................. 163

Rev. C, Advance – 07/10 ............................................................................................................................. 164

Rev. B, Advance – 03/10 .............................................................................................................................. 164

Rev. A, Advance – 03/10 .............................................................................................................................. 164

PDF: 09005aef83f3f2eb

2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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器件捷径: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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