a
FEATURES
100 MSPS Encode Rate
Very Low Input Capacitance—16 pF
Low Power—1 W
TTL Compatible Outputs
MIL-STD-883 Compliant Versions Available
APPLICATIONS
Radar Guidance
Digital Oscilloscopes/ATE Equipment
Laser/Radar Warning Receivers
Digital Radio
Electronic Warfare (ECM, ECCM, ESM)
Communication/Signal Intelligence
OVERFLOW
INHIBIT
ANALOG IN
R
V
REF
R
High-Speed 8-Bit
TTL A/D Converter
AD9012
FUNCTIONAL BLOCK DIAGRAM
AD9012
256
OVERFLOW
255
D
8
(MSB)
D
E
C
O
D
I
N
G
L
O
G
I
C
D
7
D
6
D
5
D
4
D
3
D
2
D
1
(LSB)
R
128
R/2
REF
MID
R/2
127
L
A
T
C
H
R
GENERAL DESCRIPTION
2
The AD9012 is an 8-bit, ultrahigh speed, analog-to-digital
converter. The AD9012 is fabricated in an advanced bipolar
process that allows operation at sampling rates up to one
hundred megasamples/second. Functionally, the AD9012 is
comprised of 256 parallel comparator stages whose outputs
are decoded to drive the TTL compatible output latches.
The exceptionally wide large-signal analog input bandwidth of
160 MHz is due to an innovative comparator design and very
close attention to device layout considerations. The wide input
bandwidth of the AD9012 allows very accurate acquisition of
high speed pulse inputs without an external track-and-hold.
The comparator output decoding scheme minimizes false codes,
which is critical to high speed linearity.
The AD9012 is available in two grades: one with 0.5 LSB
linearity and one with 0.75 LSB linearity. Both versions are
R
V
REF
ENCODE
1
GND
HYSTERESIS
V
S
V
S
offered in an industrial grade, –25°C to +85°C, packaged in a
28-lead DIP and a 28-lead JLCC. The military temperature
range devices, –55°C to +125°C, are available in ceramic DIP
and LCC packages and are compliant to MIL-STD-883 Class B.
The AD9012 is available in versions compliant with MIL-STD-
883. Refer to the Analog Devices Military Products Databook
or current AD9012/883B data sheet for detailed specifications.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD9012–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
RESOLUTION
DC ACCURACY
Differential Linearity
Integral Linearity
No Missing Codes
INITIAL OFFSET ERROR
Top of Reference Ladder
Bottom of Reference Ladder
Offset Drift Coefficient
ANALOG INPUT
Input Bias Current
1
Input Resistance
Input Capacitance
Large Signal Bandwidth
2
Analog Input Slew Rate
3
REFERENCE INPUT
Reference Ladder Resistance
Ladder Temperature Coefficient
Reference Input Bandwidth
DYNAMIC PERFORMANCE
Conversion Rate
Aperture Delay
Aperture Uncertainty (Jitter)
Output Delay (t
PD
)
4, 5
Transient Response
6
Overvoltage Recovery Time
7
Output Rise Time
4
Output Fall Time
4
Output Time Skew
4, 8
ENCODE INPUT
Logic “1” Voltage
4
Logic “0” Voltage
4
Logic “1” Current
Logic “0” Current
Input Capacitance
Encode Pulsewidth (Low)
9
Encode Pulsewidth (High)
9
OVERFLOW INHIBIT INPUT
0 V Input Current
AC LINEARITY
10
Effective Bits
11
In-Band Harmonics
dc to 1.23 MHz
dc to 9.3 MHz
dc to 19.3 MHz
Signal-to-Noise Ratio
12
Noise Power Ratio
13
DIGITAL OUTPUT
Logic “1” Voltage
Logic “0” Voltage
25°C
Full
25°C
Full
Full
25°C
Full
25°C
Full
Full
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
Full
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
I
VI
I
VI
VI
I
VI
I
VI
V
I
VI
I
III
V
V
VI
V
V
I
V
V
I
V
V
I
I
V
VI
VI
VI
VI
V
I
I
VI
V
I
V
V
I
V
VI
VI
I
VI
I
VI
V
V
I
48
46
Temp
8
0.75
1.0
0.6
1.0
1.2
GUARANTEED
7
6
25
60
25
200
16
160
440
80
0.25
10
100
3.8
15
4.9
8
8
6.6
3.3
3.0
200
200
25
18
15
18
10
13
0.6
(+V
S
= +5.0 V; –V
S
= –5.2 V; Differential Reference Voltage = 2.0 V; unless otherwise noted.)
AD9012BQ/BJ
Min
Typ
Max
8
0.5
0.75
0.4
0.5
1.2
GUARANTEED
7
6
25
60
200
16
160
440
80
0.25
10
100
3.8
15
4.9
8
8
6.6
3.3
3.0
200
200
25
18
15
18
10
13
0.4
AD9012SQ/SE
Min
Typ Max
8
0.75
1.0
0.6
1.0
1.2
GUARANTEED
7
6
25
60
200
16
160
440
80
0.25
10
100
3.8
15
4.9
8
8
6.6
3.3
3.0
200
200
25
18
15
18
10
13
0.6
AD9012TQ/TE
Min Typ Max
8
0.5
0.75
0.4
0.5
1.2
GUARANTEED
7
6
25
60
200
16
160
440
80
0.25
10
100
3.8
15
4.9
8
8
6.6
3.3
3.0
200
200
18
15
18
10
13
0.4
Unit
Bits
LSB
LSB
LSB
LSB
Test
AD9012AQ/AJ
Level Min Typ
Max
mV
mV
mV
mV
µV/°C
µA
µA
kΩ
pF
MHz
V/µs
Ω
Ω/°C
MHz
MSPS
ns
ps
ns
ns
ns
ns
ns
ns
V
V
µA
µA
pF
ns
ns
µA
Bits
dBc
dBc
dBc
dBc
dBc
V
V
mA
mA
mA
mA
mW
mW
mV/V
40
110
40
110
40
110
40
110
75
4
75
11
8.0
4.3
4
75
11
8.0
4.3
4
75
11
8.0
4.3
4
11
8.0
4.3
2.0
0.8
250
400
2.5
2.5
2.5
200
7.5
55
50
44
47.6
37
250
2.0
0.8
250
400
2.5
2.5
2.5
200
7.5
48
46
55
50
44
47.6
37
250
2.0
0.8
250
400
2.5
2.5
2.5
200
7.5
48
46
55
50
44
47.6
37
250
2.0
0.8
250
400
2.5
2.5
2.5
200
7.5
48
46
55
50
44
47.6
37
250
2.4
0.4
33
152
955
44
0.85
45
48
179
191
2.5
2.4
0.4
33
152
955
44
0.85
45
48
179
191
2.5
2.4
0.4
33
152
955
44
0.8
45
48
179
191
2.5
2.4
0.4
33
152
955
44
0.8
45
48
179
191
2.5
POWER SUPPLY
14
Positive Supply Current (+5.0 V) 25°C
Full
Supply Current (–5.2 V)
25°C
Full
Nominal Power Dissipation
25°C
Reference Ladder Dissipation
25°C
15
Power Supply Rejection Ratio
25°C
–2–
REV. E
AD9012
NOTES
1
Measured with Analog Input = 0 V.
2
Measured by FFT analysis where fundamental is –3 dBc.
3
Input slew rate derived from rise time (10% to 90%) of full-scale step input.
4
Outputs terminated with two equivalent ’LS00 type loads. (See load circuit.)
5
Measured from ENCODE into data out for LSB only.
6
For full-scale step input, 8-bit accuracy is attained in specified time.
7
Recovers to 8-bit accuracy in specified time, after 150% full-scale input overvoltage.
8
Output time skew includes high-to-low and low-to-high transitions as well a
s
bit-to-bit time skew differences.
9
ENCODE signal rise/fall times should be less than 30 ns for normal operation.
Measured at 75 MSPS encode rate. Harmonic data based on worst case harmonics.
11
Analog input frequency = 1.23 MHz.
12
RMS signal to rms noise, including harmonics with 1.23 MHz. analog input
signal.
13
NPR measured @ 0.5 MHz. Noise Source is 250 mW (rms) from 0.5 MHz
to 8 MHz.
14
Supplies should remain stable within
±
5% for normal operation.
15
Measured at –5.2 V
±
5% and +5.0 V
±
5%.
Specifications subject to change without notice.
10
ABSOLUTE MAXIMUM RATINGS
1
V
S
1k
TTL
OUTPUT
15pF
Positive Supply Voltage (+V
S
) . . . . . . . . . . . . . . . . . . . . . . 6 V
Analog to Digital Supply Voltage Differential (–V
S
) . . . 0.5 V
Negative Supply Voltage (–V
S
) . . . . . . . . . . . . . . . . . . . . –6 V
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . –V
S
to +0.5 V
ENCODE Input Voltage . . . . . . . . . . . . . . . . . –0.5 V to +5 V
OVERFLOW INH Input Voltage . . . . . . . . . . . –5.2 V to 0 V
Reference Input Voltage (+V
REF
–V
REF
)
2
. . . –3.5 V to +0.1 V
Differential Reference Voltage . . . . . . . . . . . . . . . . . . . . 2.1 V
Reference Midpoint Current . . . . . . . . . . . . . . . . . . . .
±
4 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
AD9012AQ/BQ/AJ/BJ . . . . . . . . . . . . . . . –25°C to +85°C
AD9012SE/SQ/TE/TQ . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature
3
. . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead Soldering Temperature (10 sec) . . . . . . . . . . . . . 300°C
NOTES
1
Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
2
+V
REF
≥
–V
REF
under all circumstances.
3
Maximum junction temperature (t
J
max) should not exceed 150°C for ceramic
and plastic packages:
t
J
= PD (θ
JA
) + t
A
PD (θ
JC
) + tc
where
PD = power dissipation
θ
JA
= thermal impedance from junction to ambient (°C/W)
θ
JC
= thermal impedance from junction to case (°C/W)
t
A
= ambient temperature (°C)
t
C
= case temperature (°C)
typical thermal impedances are:
Ceramic DIP
θ
JA
= 42°C/W;
θ
JC
= 10°C/W
Ceramic LCC
θ
JA
= 50°C/W;
θ
JC
= 15°C/W
JLCC
θ
JA
= 59°C/W;
θ
JC
= 15°C/W.
Figure 1. Load Circuit
EXPLANATION OF TEST LEVELS
Test Level
I
– 100% production tested.
II – 100% production tested at 25°C, and sample tested at
specified temperatures. AC testing done on sample basis.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – All devices are 100% production tested at 25°C. 100%
production tested at temperature extremes for extended
temperature devices; guaranteed by design and
characterization testing for industrial devices.
ORDERING GUIDE
Device
AD9012AQ
AD9012BQ
AD9012AJ
AD9012BJ
AD9012SQ
AD9012SE
AD9012TQ
AD9012TE
Linearity
0.75 LSB
0.50 LSB
0.75 LSB
0.50 LSB
0.75 LSB
0.75 LSB
0.50 LSB
0.50 LSB
Temperature
Ranges
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
Package
Options*
Q-28
Q-28
J-28A
J-28A
Q-28
E-28A
Q-28
E-28A
Recommended Operating Conditions
Parameter
–V
S
+V
S
+V
REF
–V
REF
Analog Input
Min
–5.46
+4.75
–V
REF
–2.1
–V
REF
Input Voltage
Nominal
–5.20
5.00
0.0 V
–2.0
Max
–4.94
+5.25
+0.1
+V
REF
+V
REF
*E
= Leadless Ceramic Chip Carrier; J = Ceramic Leaded Chip Carrier;
Q = Cerdip.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9012 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. E
–3–
AD9012
PIN FUNCTION DESCRIPTIONS
Pin #
11
12
Name
DIGITAL +V
S
OVERFLOW INH
Description
One of three positive digital supply pins (nominally +5.0 V).
OVERFLOW INHIBIT controls the data output coding for overvoltage inputs (AIN
≥
+ V
REF
).
ANALOG
INPUT
V
IN
≥
+ V
REF
V
IN
< + V
REF
OVERFLOW ENABLED (FLOATING)
OF D
l
D
2
D
3
D
4
D
5
D
6
D
7
D
8
1
0
0 0 0 0 0 0 0 0
X X X X X X X X
OVERFLOW INHIBITED (GND)
OF D
l
D
2
D
3
D
4
D
5
D
6
D
7
D
8
0
0
1 1 1 1 1 1 1 1
X X X X X X X X
13
14
15
16
17
18
19
10
11
12
13
14
15
16–19
20
21, 22
23
24, 25
26
27
28
HYSTERESIS
+V
REF
ANALOG INPUT
ANALOG GROUND
ENCODE
DIGITAL +V
S
ANALOG GROUND
ANALOG INPUT
–V
REF
REF
MID
DIGITAL +V
S
DIGITAL –V
S
D
1
(LSB)
D
2
–D
5
DIGITAL GROUND
ANALOG –V
S
DIGITAL GROUND
D
6
, D
7
D
8
(MSB)
OVERFLOW
DIGITAL –V
S
The Hysteresis control voltage varies the comparator hysteresis from 0 mV to 10 mV, for a
change from –5.2 V to –2.2 V at the Hysteresis control pin.
The most positive reference voltage for the internal resistor ladder.
One of two analog input pins. Both analog input pins should be connected together.
One of two analog ground pins. Both analog ground pins should be connected together.
TTL level encode command input. ENCODE is rising edge sensitive.
One of three positive digital supply pins (nominally +5.0 V).
One of two analog ground pins. Both analog ground pins should be connected together.
One of two analog input pins. Both analog inputs should be connected together.
The most negative reference voltage for the internal resistor ladder.
The midpoint tap on the internal resistor ladder.
One of three positive digital supply pins (nominally +5.0 V).
One of two negative digital supply pins (nominally –5.2 V). Both digital supply pins should be
connected together.
Digital data output. D
1
(LSB) is the least significant bit of the digital output word.
Digital data output.
One of two digital ground pins. Both digital grounds pins should be connected together.
One of two negative analog supply pins (nominally –5.2 V). Both analog supply pins should be
connected together.
One of two digital ground pins. Both digital ground pins should be connected together.
Digital data output.
Digital data output D
8
(MSB) is the most significant bit of the digital output word.
Overflow data output. Logic HIGH indicates an input overvoltage (V
IN
> + V
REF
), if
OVERFLOW INHIBIT is enabled (overflow enabled, floating). See OVERFLOW INHIBIT.
One of two negative digital supply pins (nominally –5.2 V). Both digital supply pins should be
connected together.
PIN CONFIGURATIONS
OVERFLOW INH
HYSTERESIS
DIGITAL V
S
+
DIGITAL V
S
–
OVERFLOW
OVERFLOW INH
HYSTERESIS
+V
REF
ANALOG INPUT
ANALOG GROUND
ENCODE
DIGITAL V
S
+
ANALOG GROUND
2
3
4
5
6
27
26
25
24
23
OVERFLOW
D
8
(MSB)
D
7
D
6
DIGITAL GROUND
ANALOG INPUT
5
ANALOG GROUND
6
ENCODE
7
DIGITAL V
S
+
8
ANALOG GROUND
9
ANALOG INPUT
10
–V
REF 11
4
3
2
1
28 27 26
D
8
(MSB)
25
D
7
24
D
6
23
DIGITAL GROUND
22
ANALOG V
S
–
21
ANALOG V
S
–
20
DIGITAL GROUND
19
D
5
DIGITAL V
S
+
1
28
DIGITAL V
S
–
+V
REF
TOP VIEW
22
ANALOG V
S
–
8
(Not to Scale)
21
ANALOG V
S
–
7
9
20
19
18
17
16
15
AD9012
AD9012
TOP VIEW
(Not to Scale)
DIGITAL GROUND
D
5
D
4
D
3
D
2
D
1
(LSB)
ANALOG INPUT
10
–V
REF 11
REF
MID 12
DIGITAL V
S
+
13
DIGITAL V
S
–
14
12 13 14 15 16 17 18
REF
MID
DIGITAL V
S
+
D
1
(LSB)
D
2
D
3
–4–
DIGITAL V
S
–
D
4
REV. E
AD9012
N+1
ANALOG
INPUT
N
APERTURE
DELAY
ENCODE
N+2
t
PD
OUTPUT
DATA
N–1
N
N+1
Figure 2. Timing Diagram
V
REF
R
5.0V
ANALOG
INPUT
5.0V
ENCODE
R/2
REF
MID
R/2
DIGITAL
OUTPUTS
R
5.2V
256 COMPARATOR
CELLS
V
REF
Figure 3. Input Output Circuits
DIE LAYOUT AND MECHANICAL INFORMATION
0.1 F
–5.2V
+5.0V
0.1 F
ONE JUMPER
PER BOARD
100
AD1
–V
S
+V
S
OVERFLOW
D
8
(MSB)
1k
1k
1k
1k
1k
1k
1k
1k
1k
LOAD
RESISTORS
AIN
AD9012
AD2
–2.0V
510
ENCODE
–V
REF
V
H
+V
REF
DIGITAL
GROUND
D
7
D
6
D
5
D
4
D
3
D
2
D
1
(LSB)
D
1
(LSB)
ANALOG
GROUND
ALL RESISTORS 5%
ALL CAPACITORS 20%
ALL SUPPLY VOLTAGES 5%
OPTION #1 (STATIC) AD1 = –2.0V; AD2 = +2.4V
OPTION #2 (DYNAMIC) SEE WAVEFORMS
AD1
640 s
0V
–2V
+2.4V
+0.4V
5 s
Die Dimensions . . . . . . . . . . . . . . . . 111
×
123
×
15 (± 2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
×
4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –V
S
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
Die Attach . . . . . . . . . . . . . . . . . . . . Gold Eutectic (Ceramic)
Epoxy (Plastic)
Bond Wire . . . . . . . . . . . . . 1–1.3 mil Gold; Gold Ball Bonding
AD2
Figure 4. Burn-In Diagram
REV. E
–5–
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
