RDA012M4MS DATASHEET
DS_0017PB0-2805
RDA012M4MS
12 Bit 1.3 GS/s Master-Slave 4:1 MUXDAC
Features
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
12 Bit Resolution
1.3 GS/s Sampling Rate
4:1 Input Multiplexer
Master-Slave Operation for Synchronous
Operation of Multiple Devices
Differential Analog Output
Input Code Format: Offset Binary
Output Swing: 600 mV with 50
Ω
Termination
3.3V NMOS-Compatible Data Inputs
Differential ECL or Sinusoidal Clock Input
LVDS Compatible Clock Output
10 Bit Static Linearity
Reference Output/Input Pin for Accurate
Full-Scale Adjustment.
3.3V and -5.2V Power Supply
77 Lead HSD Package
Figure 1 - Functional Block Diagram
Product Description
The RDA012M4MS is a digital-to-analog
converter (DAC) with a 4:1 input multiplexer and
a maximum update rate of 1.3GS/s. The
RDA012M4MS features master-slave operation
that simplifies synchronization when multiple
devices are required, such as in an I-Q
modulation scheme. The integrated DAC utilizes
a segmented current source to reduce the glitch
energy and achieve high linearity performance.
For best dynamic performance, the DAC outputs
are internally terminated with 50Ω resistance,
and outputs a nominal full-scale current of 12mA
when terminated with external 50Ω resistors. For
a convenient interface with most CMOS ICs, the
digital data inputs are low voltage NMOS
compatible.
Ordering information
PART NUMBER
RDA012M4MS-DI
RDA012M4MS-HD
EVRDA012M4MS-HD
DESCRIPTION
12 BIT 4:1 MUX 1.3GS/s DAC, DIE
12 BIT 4:1 MUX 1.3GS/s DAC, HSD Package
RDA012M4MS-HD Evaluation Board
Rockwell Scientific reserves the right to make changes to its product specifications at any time without notice.
The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.
Page 1 of 13
RDA012M4MS DATASHEET
DS_0017PB0-2805
Absolute Maximum Ratings
Supply Voltages
Between GNDs ……………………….……. -0.3V to +0.3V
Between VCCs …………………..………….. -0.3V to +0.3V
VCCs to GND …………………………..…….… 0V to +3.8V
RF Input Voltages
CLKIP, CLKIN to GND
........................……… 0V to VCC
HS Digital Input Voltages
DI<0:11> …...................................................... 0V to VCC
Output Termination Voltages
DOUTP, DOUTN to GND
……........................0V to VCC
Temperature
Operating Temperature………………..……. -30 to +100 °C
Case Temperature…………………………… -15 to +85 °C
Junction Temperature….……………………….….. +120 °C
Lead, Soldering (10 Seconds) ……………...…….. +220 °C
Storage………………………………………... -40 to 125 °C
Rockwell Scientific reserves the right to make changes to its product specifications at any time without notice.
The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.
Page 2 of 13
RDA012M4MS DATASHEET
DS_0017PB0-2805
Electrical Specification
PARAMETER
ACCURACY
Differential Nonlinearity
Integral Nonlinearity
DYNAMIC PERFORMANCE
Spurious Free Dynamic
Range
SYMBOL
DNL
INL
CONDITIONS, NOTE
TEST LEVEL
2
2
1
1
1
MIN
TYP
±2
±2.5
56
53
50
MAX
UNITS
LSB
LSB
dBc
dBc
dBc
dB
dB
630
0
1200
12
1260
mV
p-p
mV
mV
p-p
mA
ps
ps
ps
800
-2.0
55
mVpp
V
Ω
fF
MHz
MHz
mVpp
mV
Ω
MHz
MHz
mVpp
mV
MHz
MHz
V
V
Ω
ps
ps
SFDR1
F
clk
= 800MHz , F
out
= 267MHz
SFDR2
F
clk
= 1000MHz , F
out
= 333MHz
SFDR3
F
clk
= 1300MHz , F
out
= 400MHz
Signal Noise Ratio
SNDR
Clock Feedthrough
FD
ANALOG SIGNAL OUTPUT (OUTP, OUTN)
Single Ended, 50Ω Termination to
Full-scale Output Range
V
FSS
Ground
Single Ended, 50Ω Termination to
Full-scale Output Range
V
FSRS
Ground (MIN=000h, MAX=FFFh)
Differential with 50Ω Termination to
Full-scale output swing
V
FSD
Ground on each output
Output current
I
OUT
Rise Time
T
R,OUT
20%-80% with FSR output
Fall Time
T
F,OUT
20%-80% with FSR output
Settling Time
T
SETTL
CORE CLOCK INPUT (HCLKIP, HCLKIN)
Amplitude
V
CPP,HCLKI
Differential ECL
Common Mode Voltage
V
CM,HCLKI
Input Resistance
R
HCLKI
Input Capacitance
C
HCLKI
Maximum Frequency
F
MAX,HCLKI
Minimum Frequency
F
MIN,HCLKI
CLOCK INPUT (LCLKIP, LCLKIN)
Amplitude
V
CPP,LCLKI
Differential LVDS
Common Mode Voltage
V
CM,LCLKI
Input Resistance
R
LCLKI
Maximum Frequency
F
MAX,LCLKI
Minimum Frequency
F
MIN,LCLKI
CLOCK OUPUT (LCLKOP, LCLKON)
Amplitude
V
CPP,LCLKO
Common Mode Voltage
V
CM,LCLKO
Maximum Frequency
F
MAX,LCLKO
Minimum Frequency
F
MIN,LCLKO
DIGITAL INPUTS (A<0:11>, B<0:11>, C<0:11>, D<0:11>)
Input High Voltage
V
IH
Input Low Voltage
V
IL
Input Resistance
R
DIN
Setup Time
t
ST,DTHCK
From data input to LCLKO
Hold Time
t
HL,DTHCK
From LCLKO to data input
2
570
-650
600
2
3
1140
1
1
3
3
3
2
2
3
3
3
2
2
3
3
2
2
3
3
400
-0.8
45
1300
600
-1.5
50
1
250
0.9
325
0.25
250
0.9
325
350
1.2
450
1.5
0.25
0.9
-0.4
300
-50
VCC
0.4
350
1.2
100
450
1.5
Rockwell Scientific reserves the right to make changes to its product specifications at any time without notice.
The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.
Page 3 of 13
RDA012M4MS DATASHEET
DS_0017PB0-2805
Electrical Specification
PARAMETER
SYMBOL
CONDITIONS, NOTE
TEST LEVEL
MIN
TYP
-2.0
Internally generated
Internally generated
For externally driven VREFA, VREFD
3
3
3
-1.9
-1.9
500
3.1
-5.4
-5.4
Total dissipation
Positive supply
Negative supply, analog
Negative supply, digital
-2.0
-2.0
560
3.3
-5.2
-5.2
3300
500
500
2300
-2.1
-2.1
620
3.5
-5.0
-5.0
MAX
UNITS
V
V
V
Ω
V
V
V
mW
mW
mW
mW
°C
°C
TERMINATION (VTT)
HCLKI Termination
VTT
Voltage
REFERENCE (VREFA, VREFD)
Analog Reference
VREFA
Digital Reference
VREFD
Input Resistance
R
VREF
POWER SUPPLY
Positive Supply
VCC
Negative Supply, Analog
VEEA
Negative Supply, Digital
VEED
Power Dissipation
P
Power Dissipation
P
VCC
Power Dissipation
P
VEEA
Power Dissipation
P
VEED
OPERATING RANGE
Ambient Temperature
T
A
Junction Temperature
T
J
120
Test Levels
TEST LEVEL
1
2
3
1
TEST PROCEDURE
1,2
100% production tested at T
A
= 25C
1
Sample tested at T
A
= 25C unless other temperature is specified
Guaranteed by design and/or characterization testing
All tests are continuous, not pulsed. Therefore, Tj (junction temperature) > Tc (case temperature) > Ta (ambient temperature).
This is the normal operating condition and is more stressful than a pulsed test condition.
The tests are conducted with the power set to VCC
MIN
and to VCC
MAX
.
2
Rockwell Scientific reserves the right to make changes to its product specifications at any time without notice.
The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.
Page 4 of 13
RDA012M4MS DATASHEET
DS_0017PB0-2805
Pin Description
P/I/O
P
P
P
P
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
PIN
7, 14, 39, 62
68, 71, 72, 73, 74, 75, 76
8, 12, 26, 52, 64, 67
Bottom Plate
77
10
4
6
5
3
24
25
2
1
9, 16, 20, 27, 31, 35, 40, 44, 48, 53, 57, 61
11, 17, 21, 28, 32, 36, 41, 45, 49, 54, 58, 63
13, 18, 22, 29, 33, 37, 42, 46, 50, 55, 59, 65
15, 19, 23, 30, 34, 38, 43, 47, 51, 56, 60, 66
70
69
NUM.
4
7
6
-
1
1
1
1
1
1
1
1
1
1
12
12
12
12
1
1
NAME
VCC
VEEA
VEED
GND
VREFA
VREFD
VTT
MSM
HCLKIP
HCLKIN
LCLKIP
LCLKIN
LCLKOP
LCLKON
DIA<0:11>
DIB<0:11>
DIC<0:11>
DID<0:11>
OUTP
OUTN
FUNCTION
+3.3V Digital Power Supply
-5.2V Analog Power Supply
-5.2V Digital Power Supply
Ground
-2V Reference Voltage
Digital Circuitry Bias Reference. Bypass to Ground
HCLKI Clock Termination Voltage
Master-Slave Mode Selection:
Float - Master
GND - Slave
Clock Input
Low Clock Input
Low Clock Output
DIA<i> Is Channel A Digital Bit i Input. MSB is bit 11
DIB<i> Is Channel B Digital Bit i Input. MSB is bit 11
DIC<i> Is Channel C Digital Bit i Input. MSB is bit 11
DID<i> Is Channel D Digital Bit i Input. MSB is bit 11
Differential Output
Pin Layout (TOP view)
Figure 2 - RDA012M4MS-HD pinout (top view).
Rockwell Scientific reserves the right to make changes to its product specifications at any time without notice.
The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.
Page 5 of 13
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
