Philips Semiconductors
Product specification
N-channel TrenchMOS™ transistor
IRF540, IRF540S
FEATURES
•
’Trench’
technology
• Low on-state resistance
• Fast switching
• Low thermal resistance
SYMBOL
d
QUICK REFERENCE DATA
V
DSS
= 100 V
I
D
= 23 A
g
R
DS(ON)
≤
77 mΩ
s
GENERAL DESCRIPTION
N-channel enhancement mode field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:-
• d.c. to d.c. converters
• switched mode power supplies
• T.V. and computer monitor power supplies
The IRF540 is supplied in the SOT78 (TO220AB) conventional leaded package.
The IRF540S is supplied in the SOT404 (D
2
PAK) surface mounting package.
PINNING
PIN
1
2
3
tab
gate
drain
1
source
drain
DESCRIPTION
SOT78 (TO220AB)
tab
SOT404 (D
2
PAK)
tab
2
1 23
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
I
D
I
DM
P
D
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
T
j
= 25 ˚C to 175˚C
T
j
= 25 ˚C to 175˚C; R
GS
= 20 kΩ
T
mb
= 25 ˚C; V
GS
= 10 V
T
mb
= 100 ˚C; V
GS
= 10 V
T
mb
= 25 ˚C
T
mb
= 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
100
100
±
20
23
16
92
100
175
UNIT
V
V
V
A
A
A
W
˚C
1
It is not possible to make connection to pin:2 of the SOT404 package
August 1999
1
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS™ transistor
IRF540, IRF540S
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
E
AS
Non-repetitive avalanche
energy
Peak non-repetitive
avalanche current
CONDITIONS
Unclamped inductive load, I
AS
= 10 A;
t
p
= 350
µs;
T
j
prior to avalanche = 25˚C;
V
DD
≤
25 V; R
GS
= 50
Ω;
V
GS
= 10 V; refer
to fig:14
MIN.
-
MAX.
230
UNIT
mJ
I
AS
-
23
A
THERMAL RESISTANCES
SYMBOL PARAMETER
R
th j-mb
R
th j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
MIN.
-
SOT78 package, in free air
SOT404 package, pcb mounted, minimum
footprint
-
-
TYP. MAX. UNIT
-
60
50
1.5
-
-
K/W
K/W
K/W
ELECTRICAL CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
V
(BR)DSS
V
GS(TO)
R
DS(ON)
g
fs
I
GSS
I
DSS
Q
g(tot)
Q
gs
Q
gd
t
d on
t
r
t
d off
t
f
L
d
L
d
L
s
C
iss
C
oss
C
rss
Drain-source breakdown
voltage
Gate threshold voltage
Drain-source on-state
resistance
Forward transconductance
Gate source leakage current
Zero gate voltage drain
current
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal drain inductance
Internal source inductance
Input capacitance
Output capacitance
Feedback capacitance
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA;
T
j
= -55˚C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 175˚C
T
j
= -55˚C
V
GS
= 10 V; I
D
= 17 A
T
j
= 175˚C
V
DS
= 25 V; I
D
= 17 A
V
GS
=
±
20 V; V
DS
= 0 V
V
DS
= 100 V; V
GS
= 0 V
V
DS
= 80 V; V
GS
= 0 V; T
j
= 175˚C
I
D
= 17 A; V
DD
= 80 V; V
GS
= 10 V
MIN.
100
89
2
1
-
-
-
8.7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP. MAX. UNIT
-
-
3
-
-
49
132
15.5
10
0.05
-
-
-
-
8
39
26
24
3.5
4.5
7.5
890
139
83
-
-
4
-
6
77
193
-
100
10
250
65
10
29
-
-
-
-
-
-
-
1187
167
109
V
V
V
V
V
mΩ
mΩ
S
nA
µA
µA
nC
nC
nC
ns
ns
ns
ns
nH
nH
nH
pF
pF
pF
V
DD
= 50 V; R
D
= 2.2
Ω;
V
GS
= 10 V; R
G
= 5.6
Ω
Resistive load
Measured tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
August 1999
2
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS™ transistor
IRF540, IRF540S
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
I
S
I
SM
V
SD
t
rr
Q
rr
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
MIN.
-
-
I
F
= 28 A; V
GS
= 0 V
I
F
= 17 A; -dI
F
/dt = 100 A/µs;
V
GS
= 0 V; V
R
= 25 V
-
-
-
TYP. MAX. UNIT
-
-
0.94
61
200
23
92
1.5
-
-
A
A
V
ns
nC
August 1999
3
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS™ transistor
IRF540, IRF540S
Normalised Power Derating, PD (%)
100
90
80
70
60
50
40
30
20
10
0
0
25
50
75
100
125
Mounting Base temperature, Tmb (C)
150
175
10
Transient thermal impedance, Zth j-mb (K/W)
1
D = 0.5
0.2
0.1
0.05
0.02
single pulse
T
1E-04
1E-03
1E-02
1E-01
1E+00
P
D
0.1
tp
D = tp/T
0.01
1E-06
1E-05
Pulse width, tp (s)
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
mb
)
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Drain Current, ID (A)
9V
8V
7V
Normalised Current Derating, ID (%)
100
90
80
70
60
50
40
30
20
10
0
0
25
50
75
100
125
Mounting Base temperature, Tmb (C)
150
175
55
50
45
40
35
30
25
20
15
10
5
0
0
6V
5V
4V
1
2
3
4
5
6
7
8
9
10
Drain-Source Voltage, VDS (V)
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
mb
); conditions: V
GS
≥
10 V
Peak Pulsed Drain Current, IDM (A)
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
)
Drain-Source On Resistance, RDS(on) (Ohms)
0.8
0.7
1000
100
RDS(on) = VDS/ ID
tp = 10 us
0.6
0.5
4V
0.4
0.3
5V
0.2
0.1
VGS =9 V
5.5V
6V
6.5V
7V
8V
10
D.C.
1
100 us
1 ms
10 ms
100 ms
0.1
1
10
100
Drain-Source Voltage, VDS (V)
1000
0
0
10
20
30
Drain Current, ID (A)
40
50
Fig.3. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
)
August 1999
4
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS™ transistor
IRF540, IRF540S
Drain current, ID (A)
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
0
VDS > ID X RDS(ON)
4.5
4
3.5
3
2.5
2
175 C
Tj = 25 C
1.5
1
0.5
0
Threshold Voltage, VGS(TO) (V)
maximum
typical
minimum
1
2
3
4
5
6
7
8
9
10
-60
-40
-20
0
20
40
60
80
100 120 140 160 180
Gate-source voltage, VGS (V)
Junction Temperature, Tj (C)
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
)
Transconductance, gfs (S)
VDS > ID X RDS(ON)
Tj = 25 C
175 C
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Drain current, ID (A)
20
18
16
14
12
10
8
6
4
2
0
1.0E-01
1.0E-02
minimum
typical
1.0E-04
maximum
1.0E-05
1.0E-03
1.0E-06
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
Drain current, ID (A)
0
0.5
1
1.5
2
2.5
3
3.5
Gate-source voltage, VGS (V)
4
4.5
5
Fig.8. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
)
Normalised On-state Resistance
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
-60
-40
-20
0
20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
Capacitances, Ciss, Coss, Crss (pF)
10000
Ciss
1000
Coss
100
Crss
10
0.1
1
10
Drain-Source Voltage, VDS (V)
100
Fig.9. Normalised drain-source on-state resistance.
R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
)
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
August 1999
5
Rev 1.100
微控制器 MCU
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