out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc.
- www.issi.com
Rev. 00A
06/04/08
1
IS42SM83200D / IS42SM16160D / IS42SM32800D
IS42RM83200D / IS42RM16160D / IS42RM32800D
General Description
ISSI’s 256Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V – 2.5V
VDD and 3.3V – 2.5V VDDQ memory systems containing 268,435,456 bits. Internally configured as a quad-bank
DRAM with a synchronous interface. The 256Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving,
power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are
LVTTL (VDD = 3.3V) or LVCMOS (VDD = 2.5V) compatible. The 256Mb SDRAM has the ability to synchronously
burst data at a high data rate with automatic column-address generation, the ability to interleave between internal
banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE
function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles
and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented
starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The
registration of an Active command begins accesses, followed by a Read or Write command. The ACTIVE command
in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the
bank; A0-A12 (x8 and x16) and A0-A11 (x32) select the row). The READ or WRITE commands in conjunction with
address bits registered are used to select the starting column location for the burst access. Programmable READ or
WRITE burst lengths consist of 1, 2, 4 and 8 locations, or full page, with a burst terminate option.
FUNCTIONAL BLOCK DIAGRAM (FOR 16M
x
16
BANKS SHOWN)
CLK
CKE
CS
RAS
CAS
WE
DQML
DQMH
16
2
COMMAND
DECODER
&
CLOCK
GENERATOR
DATA IN
BUFFER
16
MODE
REGISTER
13
REFRESH
CONTROLLER
DQ 0-15
SELF
REFRESH
CONTROLLER
A10
A12
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
16
DATA OUT
BUFFER
V
DD
/V
DDQ
V
ss
/V
ss
Q
16
REFRESH
COUNTER
8192
8192
8192
8192
ROW DECODER
MULTIPLEXER
13
MEMORY CELL
ARRAY
13
ROW
ADDRESS
LATCH
13
ROW
ADDRESS
BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN
ADDRESS LATCH
9
512
(x 16)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN
ADDRESS BUFFER
COLUMN DECODER
9
2
Integrated Silicon Solution, Inc.
- www.issi.com
Rev. 00A
06/04/08
IS42SM83200D / IS42SM16160D / IS42SM32800D
IS42RM83200D / IS42RM16160D / IS42RM32800D
PIN CONFIGURATIONS
54 pin TSOP – Type II for x8
V
DD
DQ0
V
DD
Q
NC
DQ1
V
SS
Q
NC
DQ2
V
DD
Q
NC
DQ3
V
SS
Q
NC
V
DD
NC
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ7
V
SS
Q
NC
DQ6
V
DD
Q
NC
DQ5
V
SS
Q
NC
DQ4
V
DD
Q
NC
V
SS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
PIN DESCRIPTIONS
32M x 8
A0–A12
A0–A9
BA0, BA1
DQ0–DQ7
CLK
CKE
CS
RAS
Pin Name
Row Address Input
Column Address Input
Bank Select Address
Data Input/Output
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
32M x 8
CAS
WE
DQM
VDD
VSS
VDDQ
VSSQ
NC
Pin Name
Column Address Strobe Command
Write Enable
Data Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
Integrated Silicon Solution, Inc.
- www.issi.com
Rev. 00A
06/04/08
3
IS42SM83200D / IS42SM16160D / IS42SM32800D
IS42RM83200D / IS42RM16160D / IS42RM32800D
PIN CONFIGURATIONS
54 pin TSOP – Type II for x16
V
DD
DQ0
V
DD
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
DD
Q
DQ5
DQ6
V
SS
Q
DQ7
V
DD
DQML
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
V
SS
NC
DQMH
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
PIN DESCRIPTIONS
16M x16
A0–A12
A0–A8
BA0, BA1
DQ0–DQ15
CLK
CKE
CS
RAS
CAS
Pin Name
Row Address Input
Column Address Input
Bank Select Address
Data Input/Output
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
16M x16
WE
DQML / DQMH
VDD
VSS
VDDQ
VSSQ
NC
Pin Name
Write Enable
Data Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
4
Integrated Silicon Solution, Inc.
- www.issi.com
Rev. 00A
06/04/08
IS42SM83200D / IS42SM16160D / IS42SM32800D
IS42RM83200D / IS42RM16160D / IS42RM32800D
PIN CONFIGURATIONS
54-ball FBGA for x16 (Top View) (8.00mm x 13.00mm Body, 0.8mm Ball Pitch)
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