74ACT2708 64 x 9 First-In, First-Out Memory
February 1989
Revised January 1999
74ACT2708
64 x 9 First-In, First-Out Memory
General Description
The ACT2708 is an expandable first-in, first-out memory
organized as 64 words by 9 bits. An 85 MHz shift-in and 60
MHz shift-out typical data rate makes it ideal for high-speed
applications. It uses a dual port RAM architecture with
pointer logic to achieve the high speed with negligible fall-
through time.
Separate Shift-In (SI) and Shift-Out (SO) clocks control the
use of synchronous or asynchronous write or read. Other
controls include a Master Reset (MR) and Output Enable
(OE) for initializing the internal registers and allowing the
data outputs to be 3-STATE. Input Ready (IR) and Output
Ready (OR) signal when the FIFO is ready for I/O opera-
tions. The status flags HF and FULL indicate when the
FIFO is full, empty or half full.
The FIFO can be expanded to provide different word
lengths by tying off unused data inputs.
Features
s
64-words by 9-bit dual port RAM organization
s
85 MHz shift-in, 60 MHz shift-out data rate, typical
s
Expandable in word width only
s
TTL-compatible inputs
s
Asynchronous or synchronous operation
s
Asynchronous master reset
s
Outputs source/sink 8 mA
s
3-STATE outputs
s
Full ESD protection
s
Input and output pins directly in line for easy board lay-
out
s
TRW 1030 work-alike operation
Applications
• High-speed disk or tape controllers
• A/D output buffers
• High-speed graphics pixel buffer
• Video time base correction
• Digital filtering
Ordering Code:
Order Number
74ACT2708PC
Package Number
N28B
Package Description
28-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignment for DIP
Pin Descriptions
Pin Names
D
0
–D
8
MR
OE
SI
SO
IR
OR
HF
FULL
O
0
–O
8
Description
Data Inputs
Master Reset
Output Enable Input
Shift-In
Shift-Out
Input Ready
Output Ready
Half Full Flag
Full Flag
Data Outputs
FACT™ is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
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74ACT2708
Functional Description
INPUTS
Data Inputs (D
0
–D
8
)
Data inputs for 9-bit wide data are TTL-compatible. Word
width can be reduced by trying unused inputs to ground
and leaving the corresponding outputs open.
Reset (MR)
Reset is accomplished by pulsing the MR input LOW. Dur-
ing normal operation MR is HIGH. A reset is required after
power up to guarantee correct operation. On reset, the
data outputs go LOW, IR goes HIGH, OR goes LOW, FH
and FULL go LOW. During reset, both internal read and
write pointers are set to the first location in the array.
Shift-In (SI)
Data is written into the FIFO by pulsing SI HIGH. When
Shift-In goes HIGH, the data is loaded into an internal data
latch. Data setup and hold times need to be adhered to
with respect to the falling edge of SI. The write cycle is
complete after the falling edge of SI. The shift-in is inde-
pendent of any ongoing shift-out operation. After the first
word has been written into the FIFO, the falling edge of SI
makes HF go HIGH, indicating a non-empty FIFO. The first
data word appears at the output after the falling edge of SI.
After half the memory is filled, the next rising edge of SI
makes FULL go HIGH indicating a half-full FIFO. When the
FIFO is full, any further shift-ins are disabled.
When the FIFO is empty and OE is LOW, the falling edge
of the first SI will cause the first data word just shifted-in to
appear at the output, even though SO may be LOW.
Shift-Out (SO)
Data is read from the FIFO by the Shift-Out signal provided
the FIFO is not empty. SO going HIGH causes OR to go
LOW indicating that output stage is busy. On the falling
edge of SO, new data reaches the output after propagation
delay t
D
. If the last data has been shifted-out of the mem-
ory, OR continues to remain LOW, and the last word
shifted-out remains on the output pins.
Output Enable (OE)
OE LOW enables the 3-STATE output buffers. When OE is
HIGH, the outputs are in a 3-STATE mode.
Inputs
MR
H
L
SI
X
X
SO
X
X
IR
X
H
OR
X
L
Half-Full (HF)
This status flag along with the FULL status flag indicates
the degree of fullness of the FIFO. On reset, HF is LOW; it
rises on the falling edge of the first SI. The rising edge of
the SI pulse that fills up the FIFO makes HF go LOW.
Going from the empty to the full state with SO LOW, the
falling edge of the first SI causes HF to go HIGH, the rising
edge of the 33rd SI causes FULL to go HIGH, and the ris-
ing edge of the 64th SI causes HF to go LOW.
When the FIFO is full, HF is LOW and the falling edge of
the first shift-out causes HF to go HIGH indicating a “non-
full” FIFO.
Full Flag (FULL)
This status flag along with the HF status flag indicates the
degree of fullness of the FIFO. On reset, FULL is LOW.
When half the memory is filled, on the rising edge of the
next SI, the FULL flag goes HIGH. It remains set until the
difference between the write pointer and the read pointer is
less than or equal to one-half of the total memory of the
device. The FULL flag then goes LOW on the rising edge of
the next SO.
Status Flags Truth Table
HF
L
L
H
H
FULL
L
H
L
H
Full
<32
Locations Filled
≥32
Locations Filled
Status Flag Condition
Empty
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Reset Truth Table
Outputs
HF
X
L
FULL
X
L
O
0
–O
8
X
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
OUTPUTS
Data Outputs (O
0
–O
8
)
Data outputs are enabled when OE is LOW and in the 3-
STATE condition when OE is HIGH.
Input Ready (IR)
IR HIGH indicates data can be shifted-in. When SI goes
HIGH, IR goes LOW, indicating input stage is busy. IR
stays LOW when the FIFO is full and goes HIGH after the
falling edge of the first shift-out.
Output Ready (OR)
OR HIGH indicates data can be shifted-out from the FIFO.
When SO goes HIGH, OR goes LOW, indicating output
stage is busy. OR is LOW when the FIFO is reset or empty
and goes HIGH after the falling edge of the first shift-in.
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74ACT2708
MODES OF OPERATION
Mode 1: Shift in Sequence for FIFO Empty to Full
Sequence of Operation
1. Input Ready is initially HIGH; HF and FULL flags are
LOW. The FIFO is empty and prepared for valid data.
OR is LOW indicating that the FIFO is not yet ready to
output data.
2. Shift-In is set HIGH, and data is loaded into the FIFO.
Data has to be settled t
s
before the falling edge of SI
and held t
h
after.
3. Input Ready (IR) goes LOW propagation delay t
IR
after
SI goes HIGH: input stage is busy.
4. Shift-In is set LOW; IR goes HIGH indicating the FIFO
is ready for additional data. Data just shifted-in arrives
at output propagation delay t
OD5
after SI falls. OR goes
HIGH propagation delay t
IOR
after SI goes LOW, indi-
cating the FIFO has valid data on its outputs. HF goes
HIGH propagation delay t
IE
after SI falls, indicating the
FIFO is no longer empty.
5. The process is repeated through the 64th data word.
On the rising edge of the 33rd SI, FULL flag goes HIGH
propagation delay t
IHF
after SI, indicating a half-full
FIFO. HF goes LOW propagation delay t
IF
after the ris-
ing edge of the 64th pulse indicating that the FIFO is
full. Any further shift-ins are disabled.
Note:
SO and OE are LOW; MR is HIGH.
FIGURE 1. Modes of Operation Mode 1
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74ACT2708
Mode 2: Master Reset
Sequence of Operation
1. Input and Output Ready, HF and FULL can be in any
state before the reset sequence with Master Reset
(MR) HIGH.
2. Master Reset goes LOW and clears the FIFO, setting
up all essential internal states. Master Reset must be
LOW pulse width t
MRW
before rising again.
3. Master Reset rises.
4. IR rises (if not HIGH already) to indicate ready to write
state recovery time t
MRIRH
after the falling edge of MR.
Both HF and FULL will go LOW indicating an empty
FIFO, occurring recovery times t
MRE
and t
MRO
respec-
tively after the falling edge of MR. OR falls recovery
time t
MRORL
after MR falls. Data at outputs goes LOW
recovery time t
MRONL
after MR goes LOW.
5. Shift-In can be taken HIGH after a minimum recovery
time t
MRSIH
after MR goes HIGH.
FIGURE 2. Mode of Operation Mode 2
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