FAST CMOS
8-INPUT UNIVERSAL
SHIFT REGISTER
Integrated Device Technology, Inc.
IDT54/74FCT299T/AT/CT
FEATURES:
•
•
•
•
Std., A and C speed grades
Low input and output leakage
≤1µA
(max.)
CMOS power levels
True TTL input and output compatibility
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
High drive outputs (-15mA I
OH
, 48mA I
OL
)
Power off disable outputs permit “live insertion”
Meets or exceeds JEDEC standard 18 specifications
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
Available in DIP, SOIC, QSOP, CERPACK and LCC
packages
DESCRIPTION:
The IDT54/74FCT299T/AT/CT are built using an advanced
dual metal CMOS technology. The IDT54/74FCT299T/AT/
CT are 8-input universal shift/storage registers with 3-state
outputs. Four modes of operation are possible: hold (store),
shift left, shift right and load data. The parallel load inputs and
flip-flop outputs are multiplexed to reduce the total number of
package pins. Additional outputs are provided for flip-flops Q
0
and Q
7
to allow easy serial cascading. A separate active LOW
Master Reset is used to reset the register.
•
•
•
•
•
•
FUNCTIONAL BLOCK DIAGRAM
S
1
S
0
DS
7
DS
0
CP
C
D
Q
0
MR
OE
1
OE
2
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
2632 drw 01
D
Q
C
P
C
D
D
Q
C
P
C
D
D
Q
C
P
C
D
D
Q
C
P
C
D
D
Q
C
P
C
D
D
Q
C
P
C
D
D
Q
C
P
C
D
D
Q
C
P
Q
7
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995
Integrated Device Technology, Inc.
APRIL 1995
DSC-4205/4
6.11
1
IDT54/74FCT299T/AT/CT
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
S
0
OE
1
OE
2
I/O
6
I/O
4
I/O
2
I/O
0
Q
0
MR
GND
1
2
3
4
5
6
7
8
9
10
20
19
P20-1
D20-1
SO20-2
SO20-8
&
E20-1
18
17
16
15
14
13
12
11
2632 drw 02
MR
GND
DS
0
CP
I/O
1
2632 drw 03
Vcc
S
1
DS
7
Q
7
I/O
7
I/O
5
I/O
3
I/O
1
CP
DS
0
I/O
6
I/O
4
I/O
2
I/O
0
Q
0
OE
2
OE
1
S
0
Vcc
S
1
3 2
4
5
6
7
8
20 19
18
1
17
16
15
14
9 10 11 12 13
L20-2
DS
7
Q
7
I/O
7
I/O
5
I/O
3
DIP/SOIC/QSOP/CERPACK
TOP VIEW
LCC
TOP VIEW
PIN DESCRIPTION
Pin Names
CP
DS
0
DS
7
S
0
, S
1
Description
Clock Pulse Input (Active Edge Rising)
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Asynchronous Master Reset Input (Active LOW)
3-State Output Enable Inputs (Active LOW)
Parallel Data Inputs or 3-State Parallel Outputs
Serial Outputs
2632 tbl 01
FUNCTION TABLE
(1)
Inputs
MR
S
1
L
H
H
H
H
X
H
L
H
L
S
0
X
H
H
L
L
CP
X
↑
↑
↑
X
Response
Asynchronous Reset Q
0
–Q
7
= LOW
Parallel Load; I/O
n
→
Q
n
Shift Right; DS
0
→
Q
0
, Q
0
→
Q
1
, etc.
Shift Left; DS
7
→
Q
7
, Q
7
→
Q
6
, etc.
Hold
2632 tbl 02
MR
OE
1
,
OE
2
I/O
0
–I/O
7
O
0
, O
7
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑
= LOW-to-HIGH clock transition
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Commercial
(2)
Terminal Voltage
V
TERM
–0.5 to +7.0
with Respect to
GND
V
TERM(3)
Terminal Voltage
–0.5 to
with Respect to
V
CC
+0.5
GND
T
A
Operating
0 to +70
Temperature
T
BIAS
Temperature
–55 to +125
Under Bias
T
STG
Storage
–55 to +125
Temperature
P
T
Power Dissipation
0.5
I
OUT
DC Output
Current
–60 to +120
Military
–0.5 to +7.0
Unit
V
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
OUT
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max. Unit
10
pF
12
pF
2632 lnk 04
–0.5 to
V
CC
+0.5
–55 to +125
–65 to +135
–65 to +150
0.5
–60 to +120
V
°
C
°
C
°
C
W
mA
NOTE:
1. This parameter is measured at characterization but not tested.
2632 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
6.11
2
IDT54/74FCT299T/AT/CT
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V
±
5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
IH
I
IL
I
I
V
IK
I
OS
V
OH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max., V
I
= 2.7V
V
CC
= Max., V
I
= 0.5V
V
CC
= Max., V
I
= Vcc (Max.)
V
CC
= Min., I
N
= –18mA
V
CC
= Max.,
(3)
V
O
= GND
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –6mA MIL.
I
OH
= –8mA COM'L.
I
OH
= –12mA MIL.
I
OH
= –15mA COM'L.
Min.
2.0
—
—
—
—
—
–60
2.4
2.0
—
—
—
—
Typ.
(2)
—
—
—
—
—
–0.7
–120
3.3
3.0
0.3
—
200
0.01
Max.
—
0.8
±1
±1
±1
–1.2
–225
—
—
0.5
±1
—
1
Unit
V
V
µA
µA
µA
V
mA
V
V
V
µA
mV
mA
2632 tbl 05
Input LOW Current
(4)
Input HIGH Current
(4)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
V
OL
I
OFF
V
H
I
CC
Output LOW Voltage
Input/Output Power Off
Leakage
(5)
Input Hysteresis
Quiescent Power
Supply Current
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= 0V, V
IN
or V
O
≤
4.5V
—
V
CC
= Max.
V
IN
= GND or V
CC
I
OL
= 32mA MIL.
I
OL
= 48mA COM'L.
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is
±5µA
at T
A
= -55°C.
5. This parameter is guaranteed but not tested.
6.11
3
IDT54/74FCT299T/AT/CT
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply
Current TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
Vcc = Max.
V
IN
= 3.4V
(3)
Vcc = Max.
Outputs Open
OE
1
=
OE
2
= GND
MR
= V
CC
S
0
= S
1
= V
CC
DS
0
= DS
1
= GND
One Input Toggling
50% Duty Cycle
Vcc = Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
1
=
OE
2
= GND
MR
= V
CC
S
0
= S
1
= V
CC
DS
0
= DS
7
= GND
One Bit Toggling
at f
i
= 5MHz
50% Duty Cycle
Vcc = Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
1
=
OE
2
= GND
MR
= V
CC
S
0
= S
1
= V
CC
DS
0
= DS
7
= GND
Eight Bits Toggling
at f
i
= 2.5MHz
50% Duty Cycle
V
IN
= V
CC
V
IN
= GND
Test Conditions
(1)
Min.
—
—
Typ.
(2)
0.5
0.15
Max.
2.0
0.25
Unit
mA
mA/MHz
I
C
Total Power Supply
Current
(6)
V
IN
= V
CC
V
IN
= GND
—
1.5
3.5
mA
V
IN
= 3.4V
V
IN
= GND
—
2.0
5.5
V
IN
= V
CC
V
IN
= GND
—
3.8
7.3
(5)
V
IN
= 3.4V
V
IN
= GND
—
6.0
16.3
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
2632 tbl 06
6.11
4
IDT54/74FCT299T/AT/CT
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT299T
Com’l.
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
Parameter
Propagation Delay
CP to Q
0
or Q
7
Propagation Delay
CP to I/O
n
Propagation Delay
MR
to Q
0 or
Q
7
Propagation Delay
MR
to I/O
n
Output Enable Time
OE
n
to I/O
n
Output Disable Time
OE
n
to I/O
n
Set-up Time HIGH
or LOW
S
0 or S
1
to CP
Set-up Time HIGH
or LOW I/O
n
,
DS
0 or DS
7
to CP
Hold Time HIGH
or LOW
S
0 or S
1
to CP
Hold Time HIGH
or LOW I/O
n
,
DS
0 or DS
7
to CP
CP Pulse Width
HIGH or LOW
Condition
(1)
IDT54/74FCT299AT
Com’l.
(2)
IDT54/74FCT299CT
Com’l.
Min.
(2)
Mil.
(2)
Mil.
(2)
Mil.
(2)
Min.
(2)
Max. Min.
Max. Min.
Max. Min.
Max.
Max. Min
.
Max.
Unit
C
L
= 50pF
R
L
= 500Ω
2.0
2.0
2.0
2.0
1.5
1.5
7.5
10.0
12.0
10.0
15.0
11.0
7.0
—
2.0
2.0
2.0
2.0
1.5
1.5
7.5
14.0
12.0
10.5
15.0
15.0
9.0
—
2.0
2.0
2.0
2.0
1.5
1.5
3.5
7.2
7.2
7.2
8.7
6.5
6.0
—
2.0
2.0
2.0
2.0
1.5
1.5
4.0
9.5
9.5
9.5
11.5
7.5
6.5
—
2.0
2.0
2.0
2.0
1.5
1.5
3.5
6.5
6.5
6.5
6.5
6.5
6.0
—
2.0
2.0
2.0
2.0
1.5
1.5
4.0
7.5
7.5
7.5
7.5
7.5
6.5
—
ns
ns
ns
ns
ns
ns
ns
t
SU
5.5
—
5.5
—
4.0
—
4.5
—
4.0
—
4.5
—
ns
t
H
1.0
—
1.0
—
1.0
—
1.0
—
1.0
—
1.0
—
ns
t
H
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
t
W
tw
t
REM
7.0
7.0
7.0
—
—
—
7.0
7.0
7.0
—
—
—
5.0
5.0
5.0
—
—
—
6.0
6.0
6.0
—
—
—
5.0
5.0
5.0
—
—
—
6.0
6.0
6.0
—
—
—
ns
ns
ns
2619 tbl 07
MR
Pulse Width
LOW
Recovery Time
NOTES:
1. See test circuit and waveforms.
2. Minimum units are guaranteed but not tested on Propagation Delays.
6.11
5
综合技术交流
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
