ispLSI 2096V
3.3V High Density Programmable Logic
Features
• HIGH DENSITY PROGRAMMABLE LOGIC
— 4000 PLD Gates
— 96 I/O Pins, Six Dedicated Inputs
— 96 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• 3.3V LOW VOLTAGE 2096 ARCHITECTURE
— Interfaces with Standard 5V TTL Devices
— Fuse Map Compatible with 5V ispLSI 2096
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
—
f
max
= 80 MHz Maximum Operating Frequency
—
t
pd
= 10 ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
®
Functional Block Diagram
Output Routing Pool (ORP)
Output Routing Pool (ORP)
C7
A0
C6
C5
C4
C3
C2
C1
C0
Output Routing Pool (ORP)
D Q
A1
A2
GLB
D Q
ES
IG
B0
B1
B2
Logic
Array
D Q
B6
Global Routing Pool
(GRP)
B5
D Q
A3
A4
A5
A6
A7
B4
B3
D
Output Routing Pool (ORP)
Output Routing Pool (ORP)
0919/2096V
Description
20
96
VE
The ispLSI 2096V is a High Density Programmable Logic
Device containing 96 Registers, six Dedicated Input pins,
three Dedicated Clock Input pins, two dedicated Global
OE input pins and a Global Routing Pool (GRP). The
GRP provides complete interconnectivity between all of
these elements. The ispLSI 2096V features in-system
programmability through the Boundary Scan Test Ac-
cess Port (TAP). The ispLSI 2096V offers non-volatile
reprogrammability of the logic, as well as the intercon-
nect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2096V device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. C7 (see Figure 1). There are a total of 24 GLBs in the
ispLSI 2096V device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
The devices also have 96 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
U
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
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LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
2096v_10
1
Output Routing Pool (ORP)
N
S
B7
Specifications
ispLSI 2096V
Functional Block Diagram
Figure 1. ispLSI 2096V Functional Block Diagram
GOE 0
GOE 1
I/O 95
I/O 94
I/O 93
I/O 92
I/O 91
I/O 90
I/O 89
I/O 88
I/O 87
I/O 86
I/O 85
I/O 84
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
IN 5
IN 4
Input Bus
Input Bus
Output Routing Pool (ORP)
Megablock
Generic Logic
Blocks (GLBs)
C7
Output Routing Pool (ORP)
C6
C5
C4
C3
C2
C1
C0
Output Routing Pool (ORP)
Input Bus
I/O 12
I/O 13
I/O 14
I/O 15
TDI/IN 0
TMS/IN 1
EW
I/O 8
I/O 9
I/O 10
I/O 11
Input Bus
I/O 4
I/O 5
I/O 6
I/O 7
A1
A2
Global
Routing
Pool
(GRP)
Output Routing Pool (ORP)
I/O 0
I/O 1
I/O 2
I/O 3
A0
A3
Output Routing Pool (ORP)
RESET
ispEN
Output Routing Pool (ORP)
N
A4
A5
A6
A7
B0
B1
B2
B3
Input Bus
FO
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
I/O 36
I/O 37
I/O 38
I/O 39
R
Input Bus
I/O 40
I/O 41
I/O 42
I/O 43
TDO/IN 2
TCK/IN 3
I/O 44
I/O 45
I/O 46
I/O 47
CLK 0
CLK 1
CLK 2
U
Clocks in the ispLSI 2096V device are selected using the
dedicated clock pins. Three dedicated clock pins (Y0, Y1,
Y2) or an asynchronous clock can be selected on a GLB
basis. The asynchronous or Product Term clock can be
generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2096V are individually program-
mable, either as a standard totem-pole output or an
SE
is
p
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
LS
I2
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2096V device contains three Megablocks.
09
6V
E
slew rate to minimize overall output switching noise.
Device pins can be safely driven to 5-volt signal levels to
support mixed-voltage systems.
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. When this fuse is erased (JEDEC “1”),
the output is configured as a totem-pole output. When
this fuse is programmed (JEDEC “0”), the output is
configured as an open-drain. The default configuration
when the device is in bulk erased state is totem-pole
configuration. The open-drain/totem-pole option is se-
lectable through the ispDesignEXPERT software tools.
2
Y0
Y1
Y2
D
ES
IG
B7
B6
B5
B4
0917/2096V
N
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
S
Specifications
ispLSI 2096V
Absolute Maximum Ratings
1
Supply Voltage V
cc
.................................. -0.5 to +5.6V
Input Voltage Applied ............................... -0.5 to +5.6V
Off-State Output Voltage Applied ............ -0.5 to +5.6V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (T
J
) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
SYMBOL
PARAMETER
Supply Voltage
Input Low Voltage
Input High Voltage
Commercial
Industrial
EW
DC Recommended Operating Condition
D
ES
IG
MIN.
3.0
3.0
V
SS
– 0.5
2.0
3.6
3.6
0.8
5.25
pf
pf
pf
–
–
MAX.
N
N
UNITS
V
V
V
V
Table 2-0005/2096V
V
CC
V
IL
V
IH
T
A
= 0°C to + 70°C
T
A
= -40°C to + 85°C
09
6V
E
Capacitance (T
A
=25°C, f=1.0 MHz)
SYMBOL
FO
R
PARAMETER
Dedicated Input Capacitance
I/O Capacitance
TYPICAL
10
10
13
UNITS
TEST CONDITIONS
V
CC
= 3.3V, V
IN
= 2.0V
V
CC
= 3.3V, V
I/O
= 2.0V
V
CC
= 3.3V, V
Y
= 2.0V
Table 2-0006/2096V
Data Retention Specifications
Data Retention
is
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PARAMETER
LS
I2
C
1
C
2
C
3
Clock and Global Output Enable Capacitance
MINIMUM
20
10000
MAXIMUM
UNITS
Years
Cycles
Table 2-0008/2096V
ispLSI Erase/Reprogram Cycles
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Specifications
ispLSI 2096V
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.5V from
steady-state active level.
GND to 3.0V
≤
3ns 10% to 90%
1.5V
1.5V
See Figure 2
Table 2-0003/2096V
Figure 2. Test Load
+ 3.3V
R1
Device
Output
R2
CL
*
Output Load Conditions (see Figure 2)
TEST CONDITION
A
B
Active High
Active Low
Active High to Z
at
V
OH
-0.5V
Active Low to Z
at
V
OL
+0.5V
R1
316Ω
∞
316Ω
∞
316Ω
R2
348Ω
348Ω
348Ω
348Ω
348Ω
CL
35pF
35pF
35pF
5pF
5pF
*
CL includes Test Fixture and Probe Capacitance.
0213A/2128V
C
Table 2-0004/2128V
DC Electrical Characteristics
SYMBOL
PARAMETER
Output Low Voltage
Output High Voltage
Over Recommended Operating Conditions
09
6V
E
FO
R
N
EW
CONDITION
V
OL
V
OH
I
IL
I
IH
I
IL-isp
I
IL-PU
I
OS
1
I
CC
2, 4
I
OL
= 8 mA
I
OH
= -4 mA
0V
≤
V
IN
≤
V
IL
(Max.)
D
ES
IG
MIN.
–
2.4
–
–
–
–
–
–
–
TYP.
–
–
–
–
–
–
–
–
140
3
N
0.4
–
-10
10
50
-150
-150
-100
–
MAX. UNITS
V
V
µA
µA
mA
µA
µA
mA
mA
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
ispEN Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
LS
I2
(V
CC
– 0.2)V
≤
V
IN
≤
V
CC
V
≤
V
IN
≤
5.25V
CC
0V
≤
V
IN
≤
V
IL
0V
≤
V
IN
≤
V
IL
V
CC
= 3.3V, V
OUT
= 0.5V
V
IL
= 0.0V, V
IH
= 3.0V
f
CLOCK
= 1 MHz
Operating Power Supply Current
Table 2-0007A/2096V
1. One output at a time for a maximum duration of one second. V
OUT
= 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using six 16-bit counters.
3. Typical values are at V
CC
= 3.3V and T
A
= 25°C.
4. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I
CC
.
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Test
Point
Specifications
ispLSI 2096V
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST
2
#
COND.
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
B
C
–
–
1
2
3
4
5
6
7
8
9
4
DESCRIPTION
1
-80
–
–
80.0
1
-60
–
–
61.7
51.3
71.4
9.0
–
0.0
–
15.0
20.0
–
–
–
–
8.5
–
–
9.5
–
16.0
–
18.0
18.0
12.0
12.0
–
–
MIN. MAX. MIN. MAX.
10.0
15.0
–
–
–
–
UNITS
ns
ns
MHz
09
6V
E
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
1.
2.
3.
4.
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback
3
Clock Frequency with External Feedback
(
tsu2 + tco1
)
Clock Frequency, Max. Toggle
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
N
64.5
100
7.0
–
D
ES
IG
6.5
–
–
–
14.0
–
15.0
15.0
10.0
10.0
–
–
0.0
–
9.0
11.0
0.0
–
8.0
–
–
–
–
7.0
7.0
7.5
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
EW
0.0
–
7.0
–
–
–
–
5.0
5.0
N
R
FO
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
Table 2-0030/2096V
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5
S
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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