Si3241/Si3206/Si3203
Quad ProSLIC® Programmable CMOS SLIC/Codec
The Quad ProSLIC
®
is a series of low-voltage CMOS
devices that integrate both SLIC and codec
functionality into a single IC to provide a complete
four-channel analog telephone interface in
accordance with all relevant Telcordia, ITU, and ETSI
specifications. The Si3241 includes internal ringing
generation to eliminate centralized ringers and
ringing relays. On-chip subscriber loop and audio
testing allows remote diagnostics and fault detection
with no external test equipment or relays. The Quad
ProSLIC devices operate from a single 3.3 V supply
and interface to standard PCM/SPI or GCI bus digital
interfaces. The Si3206/3 linefeed interface IC
performs all high-voltage functions and operates
from a 3.3 V supply as well as three battery supplies
up to –135/–110 V. The Quad ProSLIC devices are
available in a 100-pin thin quad flat package (TQFP),
and the Si3206/3 is available in a thermally-
enhanced 48-pin thin quad flat package (TQFP) or
40-pin quad flat no-lead (QFN) package.
Description
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Software programmable parameters:
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Ringing frequency, amplitude, cadence, and wave-
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Automatic switching of up to three battery supplies
On-hook transmission
Loop or ground start operation
Smooth polarity reversal
DTMF decoder
Dual tone generators
Caller ID generator
A-Law/µ-Law companding, linear PCM
PCM and SPI bus digital interfaces with program-
mable interrupts
GCI/IOM-2 mode support
3.3 V operation
GR-909/844 loop diagnostics
Audio diagnostics with loopback
Pb-free/RoHS compliant packages
Digital loop carrier (DLC) line cards
Central office (CO) line cards
Integrated voice and data (IVD) line cards
Private Branch Exchange (PBX) systems
Key telephone systems
Optical networking terminals (ONT)
VoIP Gateways
shape
Two-wire ac impedance
Transhybrid balance
DC current loop feed (10–50 mA)
Loop closure and ring trip thresholds
Ground key detect threshold
Power alarms
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Features
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Performs all BORSCHT functions
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Ideal for applications up to 20 kft (6 km)
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Internal adaptive balanced ringing to
–135 V
PK
(Si3206) and –110 V
PK
(Si3203)
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Internal unbalanced ringing
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Power offloading
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Low power consumption
-
2.5 V
rms
pulse metering (12/16 kHz)
Applications
SLIC
CODEC
ADC
DAC
CODEC
ADC
DAC
Si3206 or Si3203
Si3206 or Si3203
RING
Linefeed
Monitor
Programmable
AC Impedance
and Hybrid
Channel 1
DTMF &
Tone Gen
Si3206 or Si3203
Si3206 or Si3203
TIP
Linefeed
Control
PCM/GCI
SPI
CODEC
ADC
DAC
CODEC
ADC
DAC
SLIC
Linefeed
Control
Linefeed
Monitor
TIP
Channel 3
RING
Caller ID
SLIC
Linefeed
Control
Linefeed
Monitor
TIP
Channel 2
RING
Ringing
Generator
Line
Diagnostics
SLIC
Linefeed
Control
Linefeed
Monitor
TIP
Channel 4
RING
DSP
ProSLIC
Copyright © 2007 by Silicon Laboratories
7.17.07
Si3241/Si3206/Si3203
Quad ProSLIC® Programmable CMOS SLIC/Codec
Selected Electrical Specifications
Parameter
Ambient Temperature
Supply Voltage, Si324x
Supply Voltage, Si3206/3
High Battery Voltage, Si3206/3
Low Battery Voltage
Maximum Loop Resistance
(loop + load)
DC Differential Output
Resistance
Idle Channel Noise
PSRR from V
DD
Longitudinal to Metallic/PCM
Balance (forward or reverse)
Metallic/PCM to Longitudinal Balance
Longitudinal Impedance
Longitudinal Current per Pin
DC Current
2-Wire Return Loss
Transhybrid Balance
Thermal Resistance, (eTQFP-100)
Continuous Power Dissipation,
(eTQFP-100)
Thermal Resistance (QFN-40)
Continuous Power Dissipation
(QFN-40)
θ
JA
P
D
θ
JA
P
D
T
A
= 85 °C
T
A
= 85 °C
Symbol
T
A
V
DD
V
DD
V
BATH
V
BATL
R
LOOP
R
DO
I
LOOP
=18 mA, V
BAT
= –48 V
I
LOOP
< I
LIM
C-Message weighted
RX and TX, dc to 3.4 kHz
200 Hz to 1 kHz
1 kHz to 3.4 kHz
200 Hz to 3.4 kHz
200 Hz to 3.4 kHz at
TIP or RING
Active off-hook
200 Hz to 3.4 kHz
V
TR
= 0 V
200 Hz to 3.4 kHz
300 Hz to 3.4 kHz
Test Condition
F-Grade
G-Grade
Min
0
–40
3.13
3.13
–9
–9
—
160
—
40
58
53
40
—
—
—
26
26
—
—
—
—
Typical
25
25
3.3
3.3
—
—
—
—
8
—
63
58
—
50
—
—
30
30
25
1.6
32
1.7
Max
70
85
3.47
3.47
–135/–110
V
BATH
2000
640
10
—
—
—
—
—
30
50
—
—
—
—
—
—
Unit
°C
°C
V
V
V
V
Ω
Ω
dBrnC
dB
dB
dB
dB
Ω
mApk
mA
dB
dB
°C/W
W
°C/W
W
Package Information
D
D1
E1
E
100
PIN 1
DESIGNATOR
A
A1
A2
b
D
D1
e
E
E1
Min
—
0.05
0.95
0.17
—
—
—
—
—
MM
Typ
—
—
—
0.22
16.00
14.00
0.50
16.00
14.00
Max
1.20
0.15
1.05
0.27
—
—
—
—
—
100-Pin ETQFP
1
e
A
A2
Bottom Side
Exposed Pad
5.0 x 5.0 mm
L
b
A1
MM
Min
A
A1
b
D
D2
e
E
E2
L
L1
aaa
bbb
ccc
ddd
Typ
Max
0.80 0.90 1.00
0.00 0.02 0.05
0.18 0.25 0.30
6.00 BSC
4.10 4.30 4.40
0.50 BSC
6.00 BSC
4.10 4.30 4.40
0.30 0.40 0.50
0.03 0.05 0.08
—
—
—
—
—
—
—
—
0.10
0.10
0.08
0.10
40-Pin QFN
ProSLIC
Copyright © 2007 by Silicon Laboratories
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders
7.17.07
嵌入式系统
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