www.fairchildsemi.com
TMC2023
CMOS Digital Output Correlator
64-Bit, 25, 30, 35, and 50 MHz
Features
•
•
•
•
•
•
•
25, 30, 35, and 50 MHz correlation rates
All inputs and outputs TTL compatible
Serial data input, parallel correlation output
Programmable word length
Independently clocked registers
Programmable threshold detection and flag output
Available in 24 pin Ceramic and Plastic DIP, 28-lead
Plastic and Ceramic chip carrier and 28-contact chip
carrier
Available to Standard Military Drawing (SMD)
Pin-Compatible with TDC1023
Output format flexibility
Three-state outputs
Low-power CMOS
Description
The TMC2023 is a monolithic 64-bit correlator with a 7-bit
three-state buffered digital output. This device consists of
three 64-bit independently clocked shift registers, one 64-bit
reference holding latch, and a 64-bit independently clocked
digital summing network. The device is available in versions
capable of 25, 30, 35, and 50 MHz parallel correlation rates.
The 7-bit threshold register allows the user to preload a
binary number from 0 to 64. Whenever the correlation is
equal to or greater than the number in the threshold register,
the threshold flag goes HIGH.
The 64-bit shift mask register (M register) allows the user to
mask or selectively to choose “no compare” bit positions,
thereby accomodating any desired word length.
The reference word is serially shifted into the B register.
Bringing LDR HIGH parallel loads the data into the R refer-
ence latch. This allows the user to serially preload a new ref-
erence word into the B register while correlation is taking
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•
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Applications
• Check sorting equipment
• High density recording
• Bar code identification
Block Diagram
CLK S
AIN
CLK A
A1
A2
A64
AOUT
INV
PIPELINED
DIGITAL
SUMMER
(3 STAGES)
7
1
LATCH
TFLG
7
LDR
R1
R2
R64
T REG
7
TS
CLK B
BIN
MIN
CLK M
M1
M2
M64
B1
B2
B64
CLK T
BOUT
MOUT
65-2023-01
IO0-6
Rev. 1.0.0
TMC2023
PRODUCT SPECIFICATION
Description
(cont.)
place between the A register and the R latch. The two words
are continually compared bit-by-bit by exclusive-OR cir-
cuits. Each exclusive-OR provides one bit to the digital sum-
mer. The output is a 7-bit word representing the number of
positions which agree at any one time between the A register
and R latch. A control provides either true or inverted binary
output formats.
Built with Fairchild Semiconductor’s one-micron double
level metal OMICRONC
™
low power CMOS process, the
TMC2023 is available in a 24-pin ceramic side brazed pack-
age, 24-pin Plastic Dual-In-Line Package, 28-contact plastic
leadless chip carrier and 28-contact chip carrier. The CMOS
TMC2023 is pin compatible with the bipolar TDC1023.
Applications
(cont.)
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•
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Radar signature recognition
Video frame synchronization
Electro-optical navigation
Pattern and character recognition
Cross-correlation control systems
Error correction coding
Asynchronous communication
Matched filtering
Cross-Correlation
When LDR goes HIGH, the B register contents are copied
into the reference latch (R latch). This useful feature allows
correlation to take place between data in the R latch and the
A register while a new reference is being serially clocked
into the B register. If the new reference is n bits long, it
requires n rising edges of CLK to load this data into the B
register. For the timing diagram, n = 64. LDR is set HIGH
during the final (n
th
) CLK B cycle, so that the new reference
word is copied into the R latch. The minimum LOW and
HIGH level pulse widths for LDR are shown as t
PWL
and
t
PWH
, respectively.
After the new reference is loaded, the data to be correlated is
clocked through the A register. Typically, CLK A and CLK S
can be tied together. This allows a new correlation score to
be computed for each shift of the A register data relative to
the fixed reference word in the R latch. The digital summer is
internally partitioned into three pipelined stages. Therefore,
a correlation score for a particular alignment of the A register
data and the R latch reference appears at the summer output
three CLK S cycles later. After an additional output delay of
t
DCOR
, the correlation data is valid at the output pins (IO
0-
6
). If this correlation result is equal to or exceeds the value in
the threshold register, then TFLG goes HIGH. TFLG is valid
t
DF
after the third rising edge of CLK S.
Functional Description
General Information
The TMC2023 consists of an input section and an output
section. The input section contains the A, B, and M registers,
an R latch, XOR/AND logic and a pipelined summer net-
work. The output section consists of threshold, inversion and
three-state logic.
Continuous Correlation
The TMC2023 contains three 1 x 64 serial shift registers (A,
B, and M). The operation of these registers is identical and
each has its own input, output, and clock. As shown in the
Timing Diagrams, valid data is loaded into register A (B, M)
on the rising edge of CLK A (CLK B, CLK M). Data is valid
if present at the input for a setup time of at least t
SSR
before
and a hold time of t
H
after the rising clock edge.
The summing process is initiated when the comparison result
between the A register and R latch is clocked into the sum-
ming network by a rising edge of CLK S. Typically, CLK A
and CLK S are tied together so that a new correlation score is
computed for each new alignment of the A register and R
latch. When LDR goes HIGH, the contents of register B are
copied into the R latch. With LDR LOW, a new template
may be entered serially into register B, while parallel corre-
lation takes place between register A and the R latch. In the
case of continuous correlation, LDR is held HIGH so that the
R latch contents continuously track those of the B register.
The summing network consists of three pipelined stages.
Therefore, the total correlation score for a given set of A and
B register contents appears at the summer output three CLK
S cycles later. Data on the output pins IO
0-6
is available after
an additional propagation delay, denoted t
DCOR
on the
Timing Diagrams.
The correlation result is compared with the contents of the
threshold register. TFLG goes HIGH if the correlation equals
or exceeds the threshold value. TFLG is valid after a delay of
t
DF
from the third CLK S rising edge.
2
Threshold Register Load
The timing sequence for loading the threshold (T) register is
shown in the Timing Diagrams. The T register holds the 7-bit
threshold value to be compared with each correlation result.
The rising edge of CLK T loads the data present on the IO
0-6
pins into the T register. T flag logic is pipelined 3 stages,
with the summer. The new value loaded into the threshold
register will affect the TFLG on the third CLK S (plus an
output delay t
DF
) following the T register load.
The output buffers must be in a high-impedance state
(disabled) when the T register is programmed from an
external source. After a delay of t
DIS
from the time TS goes
HIGH, the output buffers are disabled. The data pins IO
0-6
may then be driven externally with the new threshold data.
The data must be present for a setup time of t
SCOR
before
PRODUCT SPECIFICATION
TMC2023
and t
H
after the rising edge of CLK T for correct operation.
The minimum LOW and HIGH level pulse widths for
CLK T are shown below as t
PWL
and t
PWH
respectively.
After TS is set LOW, there is an enable delay of t
ENA
before
the internal correlation data is available at pins IO
0-6
.
register, except that its parallel outputs are ANDed with the
exclusive-ORed outputs from the A register and R latch.
Many uses of the TMC2023 digital correlator require dis-
abling the correlation between certain bit positions (A
i
and
R
i
) of input words A and R. While correlation data is being
clocked into the A and/or B register, a mask word may be
entered into the M register. Where no comparison is to be
made, zeroes are entered in those M register positions. The
exclusive-OR result between each bit position is ANDed
with a bit from the M register. Thus, if a particular mask bit
(M
i
) is zero, the output correlation between A and B for that
bit position will be disabled. Consequently, a zero correla-
tion is presented to the digital summer for each masked bit
position.
The Mask register is useful for changing correlation word
length and location within the registers. Where a word is
undefined or no correlation is to take place, the M register
should contain a zero. Conversely, it must be loaded with a
one in each position where correlation is desired
The M register is useful for building logic functions. Note
that for each bit A
i
and R
i
, the correlation logic is:
A
i
+ R
i
= A
i
R
i
+ A
i
R
i
(A
i
exclusive-OR R
i
)
This result is complemented at the input of the AND gates
and ANDed with the mask bit (M
i
) resulting in:
[A
i
R
i
+ A
i
R
i
] * M
i
The last step, performed in the digital summer, is to sum the
above result over all bit positions simultaneously for a corre-
lation at time n:
C
(
n + 3
)
=
Invert Control Timing
Most applications will tie the INVERT control HIGH or
LOW depending on system requirements. In the few situa-
tions in which the control is used dynamically, the user must
observe special timing constraints.
Because INVERT governs logic located between the master
and slave latches of the data output register, its setup and
hold requirements differ from those of the data and other
controls. The device will respond to changes on INV when-
ever CLOCK is HIGH and will ignore it when CLOCK is
LOW. To minimize the data output delay and to avoid induc-
ing errors, the user should observe the following timing con-
straints:
1.
Set INVERT to the desired state for the next output on
or before the rising edge of CLOCK. If INVERT is
asserted a few nanoseconds after the rising edge, the
data output may be similarly delayed.
More importantly, keep INVERT in the desired state
until after the falling edge of CLOCK, to avoid corrupt-
ing the output data. If INVERT is changed several nano-
seconds before the falling edge of CLOCK, the data will
likewise change. If it is changed just before the falling
edge, an indeterminate output may result.
2.
Mask Register
In addition to the A and B shift references, the TMC2023 has
another independently clocked register: the M, or mask
register. The M register functions identically to the A and B
å
i = n – 63
n
[ (
A
i
XNOR B
i
)AND
M
i
]
where i = 1, 2, 3... and n = correlation word length
Pin Assignments
M
OUT
TFLG
A
OUT
B
OUT
GND
20
V
DD
1
M
IN
2
A
IN
3
B
IN
4
CLK 5
CLK S 6
INV 7
TS 8
IO
6
9
IO
5
10
IO
4
11
IO
3
12
24 CLK B
25
24
23
22
21
23 CLK M
22 CLK A
21 LDR
20 M
OUT
19 A
OUT
18 B
OUT
17 TFLG
16 GND
15 IO
0
14 IO
1
13 IO
2
CLK A
CLK M
CLK B
V
DD
V
DD
M
IN
A
IN
26
27
28
1
2
3
4
10
11
5
6
7
8
9
19
18
17
16
15
14
13
12
NC
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
LDR
GND
IO
6
CLK T
B
IN
CLK S
INV
NC
TS
65-2023-02
3
TMC2023
PRODUCT SPECIFICATION
Pin Descriptions
Pin
Name
Power
GND
V
DD
Control
INV
Inverter Output.
Control that inverts the 7-bit digital output. When a HIGH level is
applied to this pin, the outputs IO
0-6
are logically inverted. See the Timing
Diagrams for setup and hold requirements.
10
Three-State Enable.
The three-state control enables and disables the output
buffers. A HIGH level applied to this pin forces outputs into the high impedance
state. This control also allows loading of the internal threshold register.
Load Reference.
Control that allows parallel data to be loaded from the B register
into the reference latch for correlation. If LDR is held HIGH, the R latch is
transparent.
A Register Clock.
Input clocks. Clock input pins for the A register. Each register
may be independently clocked.
M Register Clock.
Input clocks. Clock input pins for the M register. Each register
may be independently clocked.
B Register Clock.
Input clocks. Clock input pins for the B register. Each register
may be independently clocked.
Threshold Register.
Threshold register clock. Clock input used to load the T
register.
Digital Summer Clock.
Clock input that allows independent clocking of the
pipelined summer network.
Mask Register.
Mask register input. Allows the user to choose “no-compare” bit
positions. A “0” in any bit location will result in a no-compare state for that location
(bit position masked).
Shift Register.
Shift register inputs to the A 64-bit serial register.
Shift Register.
Shift register inputs to the B 64-bit serial register.
16
1
19, 20
1, 2
Ground
Supply Voltage.
The TMC2023 operates from a single +5V supply. All V
DD
and
GND pins must be connected.
J2, J7
C3, R3
Package Package
Function
TS
LDR
21
25
Clocks
CLK A
CLK M
CLK B
CLK T
CLK S
Inputs
M
IN
2
3
22
23
24
5
6
26
27
28
7
8
A
IN
B
IN
Outputs
IO
6-0
4
6
9,10,11, 11,12,
Correlation Score.
Bidirectional data pins. When outputs are enabled (TS LOW),
12,13,
13,14, data is a 7-bit binary representation of the correlation between the unmasked
14,15 15,16,17 portions of the R latch and the A register. lO
6
is the MSB. These pins also serve
as parallel inputs to load the threshold register. Data present one setup time before
CLK T goes HIGH will be latched into the threshold register.
17
18
23
24
None
21
22
19
20
5,18
Threshold Flag.
The TFLG output goes HIGH whenever the correlation score is
equal to or greater than the number loaded into the T register (0 to 64).
Shift Register B.
Shift Register A.
Shift Register M.
No Connect.
These pins should be left unconnected.
Outputs of shift registers B, A, and M, respectively.
These may be used to cascade multiple devices.
TFLG
B
OUT
A
OUT
M
OUT
No Connect
NC
4
PRODUCT SPECIFICATION
TMC2023
Absolute Maximum Ratings
(beyond which the device may be damaged)
1
Parameter
Power Supply Voltage
Input Voltage
Outputs
Applied Voltage
2
Forced Current
3,4
Short Circuit Duration
(Single output in HIGH state to GND)
Temperature
Operating, Case
Operating, Junction
Lead, Soldering (10 seconds)
Storage
-65
-60
+130
+175
+300
+150
°
C
°
C
°
C
°C
1 second
-0.5
-3.0
V
DD
+0.5
6.0
V
mA
Min.
-0.5
-0.5
Typ.
Max.
+7.0
V
DD
+0.5
Units
V
V
Notes:
1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating
conditions. Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range, and measured with respect to GND.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current, flowing into the device.
Operating Conditions
Temperature Range
Standard
Parameter
V
DD
t
PWL
Power Supply Voltage
Clock Pulse Width, LOW
TMC2023
TMC2023-1, -2
TMC2023-3
t
PWH
Clock Pulse Width, HIGH
TMC2023
TMC2023-1, -2
TMC2023-3
t
SCOR
Data Setup Time, Correlator
TMC2023
TMC2023-1, -2
TMC2023-3
t
SSR
TMC2023
TMC2023-1, -2
TMC2023-3
12
10
9
12
8
7
14
10
10
13
10
9
ns
ns
ns
ns
ns
ns
15
12
8
15
14
8
ns
ns
ns
15
12
8
15
14
10
ns
ns
ns
Min.
4.75
Nom.
5.0
Max.
5.25
Min.
4.5
Extended
Nom.
5.0
Max.
5.5
Units
Volts
Data Setup Time, Shift Register (A
IN
, B
IN
, M
IN
)
5
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