Product specifications subject to change without notice.
IDT72V3631/72V3641
3.3V CMOS SYNCFIFO™ 512 x 36 and 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (CONTINUED)
Communication between each port may take place with two 36-bit mailbox
registers. Each mailbox register has a flag to signal when new mail has been
stored. Two or more devices may be used in parallel to create wider data paths.
Expansion is also possible in word depth.
These devices are a clocked FIFO, which means each port employs a
synchronous interface. All data transfers through a port are gated to the LOW-
to-HIGH transition of a continuous (free-running) port clock by enable signals.
The continuous clocks for each port are independent of one another and can
be asynchronous or coincident. The enables for each port are arranged to
provide a simple interface between microprocessors and/or buses with
synchronous control.
The Input Ready (IR) flag and Almost-Full (AF) flag of the FIFO are two-stage
synchronized to CLKA. The Output Ready (OR) flag and Almost-Empty (AE)
flag of the FIFO are two-stage synchronized to CLKB. Offset values for the
Almost-Full and Almost-Empty flags of the FIFO can be programmed from port
A or through a serial input.
The IDT72V3631/72V3641 are characterized for operation from 0°C to
70°C. These devices are fabricated using high speed, submicron CMOS
technology.
PIN CONFIGURATION
GND
CLKA
ENA
W/RA
CSA
IR
OR
V
CC
AF
AE
VCC
MBF2
MBA
RST
GND
FS0/SD
FS1/SEN
RTM
RFM
V
CC
NC
MBB
GND
MBF1
GND
CSB
W/RB
ENB
CLKB
V
CC
A
35
A
34
A
33
A
32
V
CC
A
31
A
30
GND
A
29
A
28
A
27
A
26
A
25
A
24
A
23
GND
A
22
V
CC
A
21
A
20
A
19
A
18
GND
A
17
A
16
A
15
A
14
A
13
V
CC
A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
B
35
B
34
B
33
B
32
GND
B
31
B
30
B
29
B
28
B
27
B
26
V
CC
B
25
B
24
GND
B
23
B
22
B
21
B
20
B
19
B
18
GND
B
17
B
16
V
CC
B
15
B
14
B
13
B
12
GND
NOTE:
1. NC – No internal connection.
GND
A
11
A
10
A
9
A
8
A
7
A
6
GND
A
5
A
4
A
3
V
CC
A
2
A
1
A
0
GND
B
0
B
1
B
2
B
3
B
4
B
5
GND
B
6
V
CC
B
7
B
8
B
9
B
10
B
11
4658 drw 03
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
TQFP (PNG120, order code: PF)
TOP VIEW
2
IDT72V3631/72V3641
3.3V CMOS SYNCFIFO™ 512 x 36 and 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
A0-A35
AE
AF
B0-B35
CLKA
CLKB
CSA
CSB
ENA
ENB
FS1/
SEN,
FS0/SD
Name
Port-A Data
Almost-Empty
Flag
Almost-Full
Flag
Port-B Data
Port-A Clock
Port-B Clock
Port-A Chip
Port-B Chip
Port-A Enable
Port-B Enable
Flag-Offset
Select 1/
Serial Enable
Flag Offset 0/
Serial Data
I/O
I/O 36-bit bidirectional data port for side A.
O
O
Programmable flag synchronized to CLKB. It is LOW when the number of words in the FIFO is less than or equal to
the value in the Almost-Empty register (X).
Programmable flag synchronized to CLKA. It is LOW when the number of empty locations in the FIFO is less than or
equal to the value in the Almost-Full Offset register (Y).
CLKA is a continuous clock that synchronizes all data transfers through port-A and may be asynchronous or
coincident to CLKB. IR and
AF
are synchronous to the LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through port-B and may be asynchronous or
coincident to CLKA. OR and
AE
are synchronous to the LOW-to-HIGH transition of CLKB.
CSA
must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A. The A0-A35 Select
outputs are in the high-impedance state when
CSA
is HIGH.
CSB
must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B. The B0-B35 Select
outputs are in the high-impedance state when
CSB
is HIGH.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B.
FS1/SEN and FS0/SD are dual-purpose inputs used for flag Offset register programming. During a device reset,
FS1/SEN and FS0/SD selects the flag offset programming method. Three Offset register programming methods are
available: automatically load one of two preset values, parallel load from port A, and serial load.
When serial load is selected for flag Offset register programming, FS1/SEN is used as an enable synchronous to the
LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load the bit present on FS0/SD
into the X and Y registers. The number of bit writes required to program the Offset registers is 18/20 for the
IDT72V3631/72V3641 respectively. The first bit write stores the Y-register MSB and the last bit write stores the
X-register LSB.
IR is synchronized to the LOW-to-HIGH transition of CLKA. When IR is LOW, the FIFO is full and writes to its array
are disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the point of the
retransmit data and prevents further writes. IR is set LOW during reset and is set HIGH after reset.
A HIGH level chooses a mailbox register for a port-A read or write operation.
A HIGH level chooses a mailbox register for a port-B read or write operation. When the B0-B35 outputs are active,
a HIGH level on MBB selects data from the mail1 register for output and a LOW level selects FIFO data for output.
MBF1
is set LOW by the LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
MBF1
is set HIGH by
a LOW-to-HIGH transition of CLKB when a port-B read is selected and MBB is HIGH.
MBF1
is set HIGH by a reset.
MBF2
is set LOW by the LOW-to-HIGH transition of CLKB that writes data to the mail2 register.
MBF2
is set HIGH by
a LOW-to-HIGH transition of CLKA when a port-A read is selected and MBA is HIGH.
MBF2
is set HIGH by a reset.
OR is synchronized to the LOW-to-HIGH transition of CLKB. When OR is LOW, the FIFO is empty and reads are
disabled. Ready data is present in the output register of the FIFO when OR is HIGH. OR is forced LOW during the
reset and goes HIGH on the third LOW-to-HIGH transition of CLKB after a word is loaded to empty memory.
When the FIFO is in retransmit mode, a HIGH on RFM enables a LOW-to-HIGH transition of CLKB to reset the read
pointer to the beginning retransmit location and output the first selected retransmit data.
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while
RST
is LOW. The LOW-to-HIGH transition of
RST
latches the status of FS0 and FS1 for
AF
and
AE
offset selection.
When RTM is HIGH and valid data is present in the FIFO output register (OR is HIGH), a LOW-to-HIGH transition
of CLKB selects the data for the beginning of a retransmit and puts the FIFO in retransmit mode. The selected word
remains the initial retransmit point until a LOW- to-HIGH transition of CLKB occurs while RTM is LOW, taking the FIFO
out of retransmit mode.
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH transition of
CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH.
A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH transition of
CLKB. The B0-B35 outputs are in the high-impedance state when
W/RB
is LOW.
Description
I/O 36-bit bidirectional data port for side B.
I
I
I
I
I
I
I
IR
Input Ready
Flag
Port-A Mailbox
Select
Port-B Mailbox
Select
Mail1 Register
Flag
Mail2 Register
Flag
Output Ready
Flag
Read From
Mark
Reset
Retransmit
Mode
O
MBA
MBB
MBF1
MBF2
OR
I
I
O
O
O
RFM
RST
RTM
I
I
I
W/RA
W/RB
Port-A Write/
Read Select
Port-B Write/
Read Select
I
I
3
IDT72V3631/72V3641
3.3V CMOS SYNCFIFO™ 512 x 36 and 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)
(2)
Symbol
V
CC
V
I
(2)
V
O
(2)
I
IK
I
OK
I
OUT
I
CC
T
STG
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Input Clamp Current, (V
I
< 0 or V
I
> V
CC
)
Output Clamp Current, (V
O
= < 0 or V
O
> V
CC
)
Continuous Output Current, (V
O
= 0 to V
CC
)
Continuous Current Through V
CC
or GND
Storage Temperature Range
Rating
Commercial
–0.5 to +4.6
–0.5 to V
CC
+0.5
(3)
–0.5 to V
CC
+0.5
±20
±50
±50
±400
–65 to 150
Unit
V
V
V
mA
mA
mA
mA
°C
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
3. Control Inputs: maximum V
I
= 5.0V.
RECOMMENDED OPERATING
CONDITIONS
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
T
A
Parameter
Supply Voltage
HIGH Level Input Voltage
LOW-Level Input Voltage
HIGH-Level Output Current
LOW-Level Output Current
Operating Free-air
Temperature
Min.
3.0
2
—
—
—
0
Typ.
3.3
—
—
—
—
—
Max.
3.6
V
CC
+0.5
0.8
–4
8
70
Unit
V
V
V
mA
mA
°
C
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)
IDT72V3631
IDT72V3641
Commercial
t
CLK
= 15 ns
Typ.
(1)
—
—
—
—
—
4
8
Symbol
V
OH
V
OL
I
LI
I
LO
I
CC2
(2)
C
IN
C
OUT
Parameter
Output Logic "1" Voltage
Output Logic "0" Voltage
Input Leakage Current (Any Input)
Output Leakage Current
Standby Current
Input Capacitance
Output Capacitance
V
CC
= 3.0V,
V
CC
= 3.0V,
V
CC
= 3.6V,
V
CC
= 3.6V,
V
CC
= 3.6V,
V
I
= 0,
V
O
= 0,
Test Conditions
I
OH
= –4 mA
I
OL
= 8 mA
V
I
= V
CC
or 0
V
O
= V
CC
or 0
V
I
= V
CC
–0.2V or 0
f = 1 MHz
f = 1 MHZ
Min.
2.4
—
—
—
—
—
—
Max.
—
0.5
±5
±5
400
—
—
Unit
V
V
μA
μA
μA
pF
pF
NOTES:
1. All typical values are at V
CC
= 3.3V, T
A
= 25°C.
2. For additional I
CC
information, see Figure 1,
Typical Characteristics: Supply Current (I
CC
) vs. Clock Frequency (f
S
).
4
IDT72V3631/72V3641
3.3V CMOS SYNCFIFO™ 512 x 36 and 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The I
CC
(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT72V3641 with CLKA and CLKB set
to f
S
. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize
the graph to a zero-capacitance load. Once the capacitance load per data-output channel and the number of IDT72V3631/72V3641 inputs driven by TTL HIGH
levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With I
CC
(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
P
T
= V
CC
x I
CC(f)
+
Σ(C
L
x V
CC
2
x
f
O
)
N
where:
N = number of outputs = 36
C
L
= output capacitance load
f
O
= switching frequency of an output
When no reads or writes are occurring on these devices, the power dissipated by a single clock (CLKA or CLKB) input running at frequency f
S
is
calculated by:
P
T
= V
CC
x f
S
x 0.025 mA/MHz
175
f
data
= 1/2 f
S
T
A
= 25°C
C
L
= 0 pF
mA
150
V
CC
= 3.6V
V
CC
= 3.3V
125
Supply Current
100
V
CC
= 3.0V
75
I
CC(f)
50
25
0
0
10
20
f
S
30
40
MHz
50
60
70
4658 drw 04
Clock Frequency
Figure 1. Typical Characteristics: Supply Current (I
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