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74LVT241
3.3 V octal buffer/line driver; 3-state
Rev. 03 — 7 May 2008
Product data sheet
1. General description
The 74LVT241 high-performance BiCMOS device combines low static and dynamic power
dissipation with high speed and high output drive.
This device is an octal buffer that is ideal for driving bus lines. The device features two
output enables (1OE, 2OE), each controlling four of the 3-state outputs.
2. Features
I
I
I
I
I
I
I
3-state buffers
Octal bus interface
Input and output interface capability to systems at 5 V supply
TTL input and output switching levels
Output capability: +64 mA/−32 mA
Latch-up protection exceeds 500 mA per JESD78 class II level A
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
Bus-hold data inputs eliminate the need for external pull-up resistors for unused inputs
Live insertion/extraction permitted
Power-up 3-state
No bus current loading when output is tied to 5 V bus
I
I
I
I
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVT241D
74LVT241DB
74LVT241PW
74LVT241BQ
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
SO20
SSOP20
TSSOP20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT339-1
SOT360-1
SOT764-1
Type number
DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5
×
4.5
×
0.85 mm
NXP Semiconductors
74LVT241
3.3 V octal buffer/line driver; 3-state
4. Functional diagram
2
1A0
1Y0
18
4
1A1
1Y1
16
6
1A2
1Y2
14
8
1
1A3
1OE
1Y3
12
1
EN
18
16
14
12
2
2A0
2Y0
4
3
6
8
17
15
2A1
2Y1
5
19
7
11
EN
9
7
5
3
mna773
13
2A2
2Y2
11
19
2A3
2OE
2Y3
9
13
15
17
mna772
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVT241_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2008
2 of 16
NXP Semiconductors
74LVT241
3.3 V octal buffer/line driver; 3-state
5. Pinning information
5.1 Pinning
74LVT241
1OE
2
3
4
5
6
7
8
9
GND 10
2A3 11
GND
(1)
1
terminal 1
index area
1A0
2Y0
1OE
1A0
2Y0
1A1
2Y1
1A2
2Y2
1A3
2Y3
1
2
3
4
5
6
7
8
9
20 V
CC
19 2OE
18 1Y0
17 2A0
16 1Y1
15 2A1
14 1Y2
13 2A2
12 1Y3
11 2A3
001aah734
20 V
CC
19 2OE
18 1Y0
17 2A0
16 1Y1
15 2A1
14 1Y2
13 2A2
12 1Y3
1A1
2Y1
1A2
2Y2
1A3
2Y3
74LVT241
GND 10
001aah735
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 3.
Pin configuration for SO20 and (T)SSOP20
Fig 4.
Pin configuration for DHVQFN20
5.2 Pin description
Table 2.
Symbol
1OE
1A0 to 1A3
2A0 to 2A3
GND
1Y0 to 1Y3
2Y0 to 2Y3
2OE
V
CC
Pin description
Pin
1
2, 4, 6, 8
17, 15, 13, 11
10
18, 16, 14, 12
3, 5, 7, 9
19
20
Description
output enable input (active LOW)
data input
data input
ground (0 V)
data output
data output
output enable input (active HIGH)
supply voltage
74LVT241_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2008
3 of 16
NXP Semiconductors
74LVT241
3.3 V octal buffer/line driver; 3-state
6. Functional description
Table 3.
Inputs
1OE
L
L
H
[1]
Function table
Outputs
2OE
H
H
L
1An
L
H
X
2An
L
H
X
1Yn
L
H
Z
2Yn
L
H
Z
H = HIGH voltage level;
L = LOW voltage level;
X = Don’t care;
Z = High impedance “OFF” state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
[1]
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
j
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
storage temperature
junction temperature
total power dissipation
Conditions
[2]
Min
−0.5
−0.5
−0.5
−50
−50
-
−64
−65
-
Max
+4.6
+7.0
+7.0
-
-
128
-
+150
+150
500
Unit
V
V
V
mA
mA
mA
mA
°C
°C
mW
output in OFF or HIGH state
V
I
< 0 V
V
O
< 0 V
output in LOW state
output in HIGH state
[2]
T
amb
=
−40 °C
to +85
°C
[3]
-
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
°C.
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
For SO20 packages: above 70
°C
derate linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60
°C
derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60
°C
derate linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
I
OH
Recommended operating conditions
Parameter
supply voltage
input voltage
HIGH-level output current
Conditions
Min
2.7
0
−32
Max
3.6
5.5
-
Unit
V
V
mA
74LVT241_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 7 May 2008
4 of 16
Microchip MCU
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