IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
HIGH-PERFORMANCE
CMOS BUS
INTERFACE REGISTERS
Integrated Device Technology, Inc.
IDT54/74FCT821AT/BT/CT
IDT54/74FCT823AT/BT/CT/DT
IDT54/74FCT825AT/BT/CT
FEATURES:
• Common features:
– Low input and output leakage
≤1µA
(max.)
– CMOS power levels
– True TTL input and output compatibility
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation
Enhanced versions
– Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
– Available in DIP, SOIC, SSOP, QSOP, CERPACK
and LCC packages
• Features for FCT821T/FCT823T/FCT825T:
– A, B, C and D speed grades
– High drive outputs (-15mA I
OH
, 48mA I
OL
)
– Power off disable outputs permit “live insertion”
DESCRIPTION:
The FCT82xT series is built using an advanced dual metal
CMOS technology. The FCT82xT series bus interface regis-
ters are designed to eliminate the extra packages required to
buffer existing registers and provide extra data width for wider
address/data paths or buses carrying parity. The FCT821T
are buffered, 10-bit wide versions of the popular FCT374T
function. The FCT823T are 9-bit wide buffered registers with
Clock Enable (
EN
) and Clear (
CLR
) – ideal for parity bus
interfacing in high-performance microprogrammed systems.
The FCT825T are 8-bit buffered registers with all the FCT823T
controls plus multiple enables (
OE
1,
OE
2,
OE
3) to allow multi-
user control of the interface, e.g.,
CS
, DMA and RD/
WR
. They
are ideal for use as an output port requiring high I
OL
/I
OH
.
The FCT82xT high-performance interface family can drive
large capacitive loads, while providing low-capacitance bus
loading at both inputs and outputs. All inputs have clamp
diodes and all outputs are designed for low-capacitance bus
loading in high-impedance state.
FUNCTIONAL BLOCK DIAGRAM
D
0
EN
D
N
CLR
D
CL
Q
D
CL
Q
CP Q
CP Q
CP
OE
Y
0
Y
N
2567 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995
Integrated Device Technology, Inc
AUGUST 1995
DSC-4202/5
6.21
6.21
1
1
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
D
8
D
9
GND
NC
CP
Y
9
Y
8
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
GND
1
2
3
4 P24-1
5 D24-1
6 SO24-2
7 SO24-7
SO24-8
8
&
9
E24-1
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
CP
D
2
D
3
D
4
NC
D
5
D
6
D
7
4 3 2
1 28 27 26
5
25
6
24
7
23
8
22
L28-1
9
21
10
20
11
19
1213 14 15 16 17 18
D
1
D
0
OE
NC
V
CC
Y
0
Y
1
FCT821 10-BIT REGISTER
Y
2
Y
3
Y
4
NC
Y
5
Y
6
Y
7
2567 drw 02
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
LCC
TOP VIEW
D
8
CLR
GND
NC
CP
EN
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
CLR
GND
1
2
3
P24-1
4
D24-1
5
SO24-2
6 SO24-7
7 SO24-8
8
&
9 E24-1
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
EN
CP
D
2
D
3
D
4
NC
D
5
D
6
D
7
4 3 2
1 28 27 26
5
25
6
24
7
23
8
22
L28-1
9
21
10
20
11
19
1213 14 15 16 17 18
Y
8
D
1
D
0
OE
NC
V
CC
Y
0
Y
1
FCT823 9-BIT REGISTER
INDEX
Y
2
Y
3
Y
4
NC
Y
5
Y
6
Y
7
2567 drw 03
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
LCC
TOP VIEW
FCT825 8-BIT REGISTER
INDEX
OE
1
OE
2
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CLR
GND
24
1
23
2
22
3
4 P24-1 21
5 D24-1 20
6 SO24-2 19
7 SO24-8 18
&
17
8
E24-1 16
9
10
15
14
11
12
13
V
CC
OE
3
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
EN
CP
D
0
OE
2
OE
1
NC
V
CC
OE
3
Y
0
D
1
D
2
D
3
NC
D
4
D
5
D
6
1 28 27 26
5
25
6
24
7
23
8
22
L28-1
9
21
10
20
11
19
1213 14 15 16 17 18
D
7
CLR
GND
NC
CP
EN
Y
7
4 3 2
Y
1
Y
2
Y
3
NC
Y
4
Y
5
Y
6
2567 drw 04
DIP/SOIC/QSOP/CERPACK
TOP VIEW
6.21
LCC
TOP VIEW
2
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Names
D
I
CLR
FUNCTION TABLE
(1)
Inputs
OE
CLR
EN
I/O
I
I
Description
The D flip-flop data inputs.
When the clear input is LOW and
OE
is
LOW, the Q
I
outputs are LOW. When
the clear input is HIGH, data can be
entered into the register.
Clock Pulse for the Register; enters
data into the register on the LOW-to-
HIGH transition.
The register 3-state outputs.
Clock Enable. When the clock enable is
LOW, data on the D
I
input is transferred
to the Q
I
output on the LOW-to-HIGH
clock transition. When the clock enable
is HIGH, the Q
I
outputs do not change
state, regardless of the data or clock
input transitions.
Output Control. When the
OE
input is
HIGH, the Y
I
outputs are in the high-
impedance state. When the
OE
input is
LOW, the TRUE register data is present
at the Y
I
outputs.
2567 tbl 01
D
I
L
H
X
X
X
X
L
H
L
H
CP
↑
↑
X
X
X
X
↑
↑
↑
↑
Internal/
Outputs
Q
I
Y
I
L
H
L
L
NC
NC
L
H
L
H
Z
Z
Z
L
Z
NC
Z
Z
L
H
H
H
H
L
H
L
H
H
L
L
H
H
L
L
H
H
H
H
H
H
L
L
X
X
H
H
L
L
L
L
Function
High Z
Clear
Hold
Load
CP
I
Y
I
EN
O
I
OE
I
NOTE:
1. H = HIGH
L = LOW
X = Don’t Care
NC = No Change
↑
= LOW-to-HIGH Transition
Z = High Impedance
2567 tbl 02
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Commercial
(2)
Terminal Voltage
V
TERM
–0.5 to +7.0
with Respect to
GND
V
TERM(3)
Terminal Voltage
–0.5 to
with Respect to
V
CC
+0.5
GND
T
A
Operating
0 to +70
Temperature
T
BIAS
Temperature
–55 to +125
Under Bias
T
STG
Storage
–55 to +125
Temperature
P
T
Power Dissipation
0.5
I
OUT
DC Output
Current
–60 to +120
Military
–0.5 to +7.0
Unit
V
CAPACITANCE
(
T
A
= +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
OUT
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max. Unit
10
pF
12
pF
2567 lnk 04
–0.5 to
V
CC
+0.5
–55 to +125
–65 to +135
–65 to +150
0.5
–60 to +120
V
°C
°C
°C
W
mA
NOTE:
1. This parameter is measured at characterization but not tested.
2567 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
6.21
3
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V
±
5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
I H
I
I L
I
OZH
I
OZL
I
I
V
IK
V
H
I
CC
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Input LOW Current
(4)
High Impedance Output Current
(3-State Output pins)
(4)
Input HIGH Current
(4)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Min., I
IN
= –18mA
—
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
I
= 2.7V
V
I
= 0.5V
V
O
= 2.7V
V
O
= 0.5V
V
CC
= Max., V
I
= V
CC
(Max.)
Min.
2.0
—
—
—
—
—
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
–0.7
200
0.01
Max.
—
0.8
Unit
V
V
±
1
±
1
±
1
±
1
±
1
–1.2
—
1
µ
A
µ
A
µ
A
V
mV
mA
2567 lnk 05
V
CC
= Max., V
IN
= GND or V
CC
OUTPUT DRIVE CHARACTERISTICS FOR FCT821/823/825T
Symbol
V
OH
Parameter
Output HIGH Voltage
Test Conditions
(1)
V
CC
= Min.
I
OH
= –6mA MIL.
V
IN
= V
IH
or V
IL
I
OH
= –8mA COM'L.
I
OH
= –12mA MIL.
I
OH
= –15mA COM'L.
V
CC
= Min.
I
OL
= 32mA MIL.
V
IN
= V
IH
or V
IL
I
OL
= 48mA COM'L.
V
CC
= Max., V
O
= GND
(3)
V
CC
= 0V, V
IN
or V
O
≤
4.5V
Min.
2.4
2.0
—
–60
—
Typ.
(2)
3.3
3.0
0.3
–120
—
Max.
—
—
0.5
–225
±1
Unit
V
V
V
mA
µA
2567 lnk 06
V
OL
I
OS
I
OFF
Output LOW Voltage
Short Circuit Current
Input/Output Power Off Leakage
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is
±5µA
at T
A
= –55°C.
5. This parameter is guaranteed but not tested.
6.21
4
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
OE
=
EN
= GND
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
=
EN
= GND
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
=
EN
= GND
Eight Bits Toggling
at fi = 2.5MHz
50% Duty Cycle
Min.
—
V
IN
= V
CC
V
IN
= GND
—
Typ.
(2)
0.5
0.15
Max.
2.0
0.25
Unit
mA
mA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
—
1.5
3.5
mA
V
IN
= 3.4V
V
IN
= GND
—
2.0
5.5
V
IN
= V
CC
V
IN
= GND
—
3.8
7.3
(5)
V
IN
= 3.4V
V
IN
= GND
—
6.0
16.3
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP/
2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
2567 tbl 07
6.21
5
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
