noted. All specifications T to T unless otherwise noted. Specifications
0.)
DD
REF
MIN
MAX
REF
(–)
= GND = O V unless otherwise
Parameter
ACCURACY
Resolution
Total Unadjusted Error
2
Minimum Resolution for which
No Missing Codes Are Guaranteed
Channel-to-Channel Mismatch
REFERENCE INPUT
Input Resistance
V
REF
(+) Input Voltage Range
V
REF
(–) Input Voltage Range
ANALOG INPUT
Input Voltage Range
Input Leakage Current
Input Capacitance
3
LOGIC INPUTS
RD, CS,
A0, A1 & A2
V
INH
V
INL
I
INH
I
INL
Input Capacitance
3
LOGIC OUTPUTS
DB0–DB7 &
INT
V
OH
V
OL
I
OUT
(DB0–DB7)
Output Capacitance
3
RDY
V
OL4
I
OUT
Output Capacitance
SLEW RATE, TRACKING
3
POWER SUPPLY
V
DD
I
DD5
Power Dissipation
Power Supply Sensitivity
NOTES
1
Temperature ranges are as follows:
K Version
1
L Version B, T Versions
8
±
1
8
±
1/4
1.0/4.0
V
REF
(–)/
V
DD
GND/
V
REF
(+)
V
REF
(–)/
V
REF
(+)
±
3
45
8
±
1/2
8
±
1/4
1.0/4.0
V
REF
(–)/
V
DD
GND/
V
REF
(+)
V
REF
(–)/
V
REF
(+)
±
3
45
8
±
1
8
±
1/4
1.0/4.0
V
REF
(–)/
V
DD
GND/
V
REF
(+)
V
REF
(–)/
V
REF
(+)
±
3
45
C, U Versions Unit
8
±
1/2
8
±
1/4
1.0/4.0
V
REF
(–)/
V
DD
GND/
V
REF
(+)
V
REF
(– )/
V
REF
(+)
±
3
45
Bits
LSB max
Bits
LSB max
kΩ min/kΩ max
V min/V max
V min/V max
Conditions/Comments
V min/V max
µA
max
pF typ
Analog Input Any Channel
0 V to 5 V
2.4
0.8
1
–1
8
2.4
0.8
1
–1
8
2.4
0.8
1
–1
8
2.4
0.8
1
–1
8
V min
V max
µA
max
µA
max
pF max
Typically 5 pF
4.0
0.4
±
3
8
0.4
±
3
8
0.7
0.157
5
16
50
80
±
1/4
4.0
0.4
±
3
8
0.4
±
3
8
0.7
0.157
5
16
50
80
±
1/4
4.0
0.4
±
3
8
0.4
±
3
8
0.7
0.157
5
20
50
100
±
1/4
4.0
0.4
±
3
8
0.4
±
3
8
0.7
0.157
5
20
50
100
±
1/4
V min
V max
µA
max
pF max
V max
µA
max
pF max
V/µs typ
V/µs max
Volts
mA max
mW typ
mW max
LSB max
I
SOURCE
= 360
µA
I
SINK
= 1.6 mA
Floating State Leakage
Typically 5 pF
I
SINK
= 2.6 mA
Floating State Leakage
Typically 5 pF
±
5% for Specified
Performance
CS
=
RD
= 2.4 V
±
1/16 LSB typ
V
DD
= 5 V
±
5%
K, L Versions; 0°C to 70°C
B, C Versions; –40°C to +85°C
T, U Versions; –55°C to +125°C
2
Total Unadjusted Error includes offset, full-scale and linearity errors.
3
Sample tested at 25°C by Product Assurance to ensure compliance.
4
RDY is an open drain output.
5
See Typical Performance Characteristics.
Specifications subject to change without notice.
–2–
REV. D
AD7824/AD7828
TIMING CHARACTERISTICS
1
(V
Parameter
t
CSS
t
CSH
t
AS
t
AH
t
RDY2
t
CRD
t
ACC13
t
ACC23
t
lNTH2
t
DH4
t
P
t
RD
Limit at 25 C
(All Grades)
0
0
0
30
40
2.0
85
50
40
75
60
500
60
600
DD
= 5 V; V
REF
(+) = 5 V; V
REF
(–) = GND = 0 V unless otherwise noted)
Limit at
T
MIN
, T
MAX
(T, U Grades)
0
0
0
40
60
2.8
120
70
70
100
70
600
80
400
Limit at
T
MIN
, T
MAX
(K, L, B, C Grades)
0
0
0
35
60
2.4
110
60
65
100
70
500
80
500
Unit
ns min
ns min
ns min
ns min
ns max
µs
max
ns max
ns max
ns typ
ns max
ns max
ns min
ns min
ns max
Conditions/Comments
CS
to
RD
Setup Time
CS
to
RD
Hold Time
Multiplexer Address Setup Time
Multiplexer Address Hold Time
CS
to RDY Delay. Pull-Up
Resistor 5 kΩ.
Conversion Time, Mode 0
Data Access Time after
RD
Data Access Time after
INT,
Mode 0
RD
to
INT
Delay
Data Hold Time
Delay Time between Conversions
Read Pulsewidth, Mode 1
NOTES
1
Sample tested at 25°C to ensure compliance. All input control signals are specified with tr = tf = 20 ns (10 % to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
C
L
= 50 pF.
3
Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
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