VCXO JITTER ATTENUATOR &
FEMTOCLOCK™ MULTIPLIER
ICS810252I-03
NRND
G
ENERAL
D
ESCRIPTION
The ICS810252I-03 is a member of the
HiPerClockS™
HiperClockS™ family of high performance clock
solutions from IDT. The ICS810252I-03 is a PLL
based synchronous multiplier that is optimized for
PDH or SONET to Ethernet clock jitter attenuation
and frequency translation. The device contains two internal
frequency multiplication stages that are cascaded in series.
The first stage is a VCXO PLL that is optimized to provide
reference clock jitter attenuation. The second stage is a
FemtoClock™ frequency multiplier that provides the low jitter,
high frequency Ethernet output clock that easily meets Gigabit
and 10 Gigabit Ethernet jitter requirements. Pre-divider and
output divider multiplication ratios are selected using device
selection control pins. The multiplication ratios are optimized
to support most common clock rates used in PDH, SONET
and Ethernet applications. The VCXO requires the use of an
external, inexpensive pullable crystal. The VCXO uses external
passive loop filter components which allows configuration of
the PLL loop bandwidth and damping characteristics. The
device is packaged in a space-saving 32-VFQFN package and
supports industrial temperature range.
F
EATURES
•
Two LVCMOS/LVTTL outputs, 17Ω impedance
Each output supports independent frequency selection at
25MHz, 62.5MHz, 125MHz, and 156.25MHz
•
Two differential inputs support the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
Accepts input frequencies from 8kHz to 155.52MHz including
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,
125MHz and 155.52MHz
•
Attenuates the phase jitter of the input clock by using a low-
cost pullable fundamental mode VCXO crystal
•
VCXO PLL bandwidth can be optimized for jitter attenuation
and reference tracking
using external loop filter connection
•
FemtoClock frequency multiplier provides low jitter, high
frequency output
•
Absolute pull range: ±50ppm
•
FemtoClock VCO frequency: 625MHz
•
RMS phase jitter @ 125MHz, using a 25MHz crystal
(12kHz - 20MHz): 1.3ps (typical)
•
3.3V supply voltage
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
•
Not Recommended for New Designs. This part is being
replaced by ICS810252BKI-03 / ICS810252BYI-03
IC
S
XTAL_OUT
P
IN
A
SSIGNMENT
V
DDX
32 31 30 29 28 27 26 25
LF1
LF0
ISET
GND
CLK_SEL
V
DD
RESERVED
GND
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
PDSEL_2
PDSEL_1
PDSEL_0
V
DDA
V
DD
ODBSEL_1
ODBSEL_0
ODASEL_1
ICS810252I-03
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
32-Lead TQFP, E-Pad
7mm x 7mm x 1.0mm package body
Y package
Top View
IDT
™
/ ICS
™
VCXO JITTER ATTENUATOR/MULTIPLIER
XTAL_IN
nCLK0
nCLK1
CLK0
CLK1
V
DD
24
23
22
21
20
19
18
17
GND
V
DDO
_
QB
QB
GND
V
DDO
_
QA
QA
GND
ODASEL_0
1
ICS810252AKI-03 REV. A JANUARY 13, 2009
ICS810252I-03
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3
4, 8, 18,
21, 24
5
6, 12, 27
7
9,
10 ,
11
13
14,
15
16,
17
19
20
22
23
25
26
28
29
30,
31
32
Name
LF1, LF0
ISET
GND
CLK_SEL
V
DD
RESERVED
PDSEL_2,
PDSEL_1,
PDSEL_0
V
DDA
ODBSEL_1,
ODBSEL_0
ODASEL_1,
ODASEL_0
QA
V
DDO_QA
QB
V
DDO_QB
nCLK1
CLK1
nCLK0
CLK0
XTAL_OUT,
XTAL_IN
V
DDX
Type
Analog
Input/Output
Analog
Input/Output
Power
Input
Power
Reser ved
Input
Power
Input
Input
Output
Power
Output
Power
Input
Input
Input
Input
Input
Power
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup
Pulldown
Description
Loop filter connection node pins.
Charge pump current setting pin.
Power supply ground.
Input clock select. When HIGH selects CLK1/nCLK1.
When LOW, selects CLK0/nCLK0. LVCMOS/LVTTL interface levels.
Core power supply pins.
Reser ved pin. Do not connect.
Pre-divider select pins. LVCMOS/LVTTL interface levels.
See Table 3A.
Analog supply pin.
Frequency select pins for Bank B output. See Table 3B.
Pulldown
LVCMOS/LVTTL interface levels.
Frequency select pins for Bank A output. See Table 3B.
Pulldown
LVCMOS/LVTTL interface levels.
Bank A single-ended clock output. LVCMOS/LVTTL interface levels.
17
Ω
output impedance.
Output power supply pin for QA clock output.
Bank B single-ended clock output. LVCMOS/LVTTL interface levels.
17
Ω
output impedance.
Output power supply pin for QB clock output.
Inver ting differential clock input. V
DD
/2 bias voltage when left floating.
Non-inver ting differential clock input.
Inver ting differential clock input. V
DD
/2 bias voltage when left floating.
Non-inver ting differential clock input.
Cr ystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Power supply pin for VCXO charge pump.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
Minimum Typical
4
V
DD
, V
DDX
, V
DDO_QA,
V
DDO_QB
= 3.465V
10
51
51
17
Maximum
Units
pF
pF
kΩ
kΩ
Ω
IDT
™
/ ICS
™
VCXO JITTER ATTENUATOR/MULTIPLIER
3
ICS810252AKI-03 REV. A JANUARY 13, 2009
ARM技术
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