IMPORTANT NOTICE
Dear customer,
As from August 2
nd
2008, the wireless operations of NXP have moved to a new company,
ST-NXP Wireless.
As a result, the following changes are applicable to the attached document.
●
Company name - NXP B.V.
is replaced with
ST-NXP Wireless.
Copyright
- the copyright notice at the bottom of each page “© NXP B.V. 200x. All
rights reserved”, shall now read: “© ST-NXP Wireless 200x - All rights reserved”.
Web site
-
http://www.nxp.com
is replaced with
http://www.stnwireless.com
Contact information
- the list of sales offices previously obtained by sending
an email to
salesaddresses@nxp.com
, is now found at
http://www.stnwireless.com
under Contacts.
●
●
●
If you have any questions related to the document, please contact our nearest sales office.
Thank you for your cooperation and understanding.
ST-NXP Wireless
www.stnwireless.com
ISP1507C; ISP1507D
ULPI Hi-Speed Universal Serial Bus host and peripheral
transceiver
Rev. 01 — 28 May 2008
Product data sheet
1. General description
The ISP1507 is a Universal Serial Bus (USB) high-speed host and peripheral transceiver
that is fully compliant with
Universal Serial Bus Specification Rev. 2.0
and
UTMI+ Low Pin
Interface (ULPI) Specification Rev. 1.1.
The ISP1507 can transmit and receive USB data at high-speed (480 Mbit/s), full-speed
(12 Mbit/s) and low-speed (1.5 Mbit/s), and provides a pin-optimized, physical layer
front-end attachment to USB host, peripheral and OTG devices.
It is ideal for use in portable electronic devices, such as mobile phones, digital still
cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio
players. It allows USB Application-Specific Integrated Circuits (ASICs), Programmable
Logic Devices (PLDs) and any system chip set to interface with the physical layer of the
USB through a 12-pin interface.
The ISP1507 can interface to the link with digital I/O voltages in the range of 1.65 V to
3.6 V.
The ISP1507 is available in HVQFN24 package.
2. Features
I
Fully complies with:
N
Universal Serial Bus Specification Rev. 2.0
N
UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1
I
Interfaces to host and peripheral cores; optimized for stand-alone and embedded host
applications with an external V
BUS
supply; stand-alone peripheral cores, and Session
Request Protocol (SRP)-capable peripheral cores
I
Complete Hi-Speed USB physical front-end solution that supports high-speed
(480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
N
Integrated 45
Ω ±
10 % high-speed termination resistors, 1.5 kΩ
±
5 % full-speed
device pull-up resistor, and 15 kΩ
±
5 % host termination resistors
N
Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive
N
USB clock and data recovery to receive USB data up to
±500
ppm
N
Insertion of stuff bits during transmit and discarding of stuff bits during receive
N
Non-Return-to-Zero Inverted (NRZI) encoding and decoding
N
Supports bus reset, suspend, resume and high-speed detection handshake (chirp)
I
Supports SRP for reduced power consumption
N
Complete control over bus resistors
N
Data line and V
BUS
pulsing session request methods
NXP Semiconductors
ISP1507C; ISP1507D
ULPI HS USB host and peripheral transceiver
I
I
I
I
I
N
Integrated V
BUS
voltage comparators
Highly optimized ULPI compliant
N
60 MHz, 8-bit interface between the core and the transceiver
N
Supports 60 MHz output clock configuration
N
Integrated Phase-Locked Loop (PLL) supporting one crystal or clock frequency:
19.2 MHz (ISP1507CBS) and 26 MHz (ISP1507DBS)
N
Fully programmable ULPI-compliant register set
N
Internal Power-On Reset (POR) circuit
Flexible system integration and very low current consumption, optimized for portable
devices
N
Power-supply input range is 3.0 V to 3.6 V
N
Internal voltage regulator supplies 3.3 V and 1.8 V
N
Supports external V
BUS
charge pump
N
External V
BUS
source is controlled using the PSW_N pin; open-drain PSW_N
allows per-port or ganged power control
N
FAULT input pin to monitor the external V
BUS
supply status
N
Supports wide range interfacing I/O voltage of 1.65 V to 3.6 V; separate I/O voltage
pins minimize crosstalk
N
Typical operating current of 10 mA to 48 mA, depending on the USB speed and
bus utilization
N
Typical suspend current of 35
µA
Full industrial grade operating temperature range from
−40 °C
to +85
°C
4 kV ElectroStatic Discharge (ESD) protection on pins DP, DM, V
BUS
and GND
Available in a small HVQFN24 (4 mm
×
4 mm) Restriction of Hazardous Substances
(RoHS) compliant, halogen-free and lead-free package
3. Applications
I
I
I
I
Digital still camera
Digital TV
Digital Video Disc (DVD) recorder
External storage device, for example:
N
Magneto-Optical (MO) drive
N
Optical drive: CD-ROM, CD-RW, DVD
N
Zip drive
Mobile phone
MP3 player
PDA
Printer
Scanner
Set-Top Box (STB)
Video camera
I
I
I
I
I
I
I
ISP1507C_ISP1507D_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 28 May 2008
2 of 74
NXP Semiconductors
ISP1507C; ISP1507D
ULPI HS USB host and peripheral transceiver
4. Ordering information
Table 1.
Part
Type number
Marking
Ordering information
Package
Crystal or Name
clock
frequency
19.2 MHz
26 MHz
HVQFN24
HVQFN24
Description
Version
ISP1507CBS
ISP1507DBS
507C
[1]
507D
[1]
plastic thermal enhanced very thin quad flat package; SOT616-3
no leads; 24 terminals; body 4
×
4
×
0.85 mm
plastic thermal enhanced very thin quad flat package; SOT616-3
no leads; 24 terminals; body 4
×
4
×
0.85 mm
[1]
The package marking is the first line of text on the IC package and can be used for IC identification.
ISP1507C_ISP1507D_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 28 May 2008
3 of 74
NXP Semiconductors
ISP1507C; ISP1507D
ULPI HS USB host and peripheral transceiver
5. Block diagram
CLOCK
STP
DIR
ULPI
INTERFACE
NXT
8
21
15
14
16
1, 2,
17 to 20,
22, 24
ULPI
INTERFACE
CONTROLLER
USB DATA
SERIALIZER
6
HIGH-SPEED
USB ATX
TERMINATION
RESISTORS
5
DP
USB DATA
DESERIALIZER
V
BUS
VALID EXTERNAL
DRIVE V
BUS
EXTERNAL
DM
DATA
[7:0]
REGISTER
MAP
USB
CABLE
RESET_N/
PSW_N
12
GLOBAL
RESET
POWER-ON
RESET
V
BUS
COMPARATORS
8
V
BUS
/
FAULT
PLL
GLOBAL
CLOCKS
XTAL1
XTAL2
V
CC(I/O)
10
11
3, 23
CRYSTAL
OSCILLATOR
SRP CHARGE
AND DISCHARGE
RESISTORS
interface voltage
internal power
ISP1507
BAND GAP
REFERENCE
VOLTAGE
4
REG3V3
REG1V8
VCC
9
13
7
VOLTAGE
REGULATOR
V
REF
RREF
004aab078
Fig 1.
Block diagram
ISP1507C_ISP1507D_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 28 May 2008
4 of 74
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