IMPORTANT NOTICE
Dear customer,
As from February 2nd 2009, ST and Ericsson have merged Ericsson Mobile
Platforms and ST‐NXP Wireless into a 50/50 joint venture "ST‐Ericsson".
As a result, the following changes are applicable to the attached
document.
● Company name ‐ ST‐NXP Wireless is replaced with ST‐Ericsson.
● Copyright ‐ the copyright notice at the bottom of each page “© ST‐NXP
Wireless 200x ‐ All rights reserved”, shall now read: “© ST‐Ericsson, 2009 ‐
All rights reserved”.
● Web site ‐ http://www.stnwireless.com is replaced with
www.stericsson.com
● Contact information ‐ the list of sales offices previously obtained at
http://www.stnwireless.com , is now found at www.stericsson.com
under Contacts
If you have any questions related to the document, please contact our
nearest sales office.
Thank you for your cooperation and understanding.
ISP1507A; ISP1507B
ULPI Hi-Speed USB On-The-Go transceiver
Rev. 02 — 19 January 2009
Product data sheet
1. General description
The ISP1507 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully
compliant with
Universal Serial Bus Specification Rev. 2.0, On-The-Go Supplement to the
USB 2.0 Specification Rev. 1.3
and
UTMI+ Low Pin Interface (ULPI) Specification
Rev. 1.1.
The ISP1507 can transmit and receive USB data at high-speed (480 Mbit/s), full-speed
(12 Mbit/s) and low-speed (1.5 Mbit/s), and provides a pin-optimized, physical layer
front-end attachment to USB host, peripheral and OTG devices.
It is ideal for use in portable electronic devices, such as mobile phones, digital still
cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio
players. It allows USB Application-Specific Integrated Circuits (ASICs), Programmable
Logic Devices (PLDs) and any system chip set to interface with the physical layer of the
USB through a 12-pin interface.
The ISP1507 can interface to the link with digital I/O voltages in the range of 1.65 V to
3.6 V.
The ISP1507 is available in HVQFN32 package.
2. Features
Fully complies with:
Universal Serial Bus Specification Rev. 2.0
On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3
UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1
Interfaces to host, peripheral and OTG device cores; optimized for portable devices or
system ASICs with built-in USB OTG device core
Complete Hi-Speed USB physical front-end solution that supports high-speed
(480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
Integrated 45
Ω ±
10 % high-speed termination resistors, 1.5 kΩ
±
5 % full-speed
device pull-up resistor, and 15 kΩ
±
5 % host termination resistors
Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive
USB clock and data recovery to receive USB data up to
±500
ppm
Insertion of stuff bits during transmit and discarding of stuff bits during receive
Non-Return-to-Zero Inverted (NRZI) encoding and decoding
Supports bus reset, suspend, resume and high-speed detection handshake (chirp)
Complete USB OTG physical front-end that supports Host Negotiation Protocol (HNP)
and Session Request Protocol (SRP)
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
Integrated 5 V charge pump; also supports external charge pump or 5 V V
BUS
switch
Complete control over bus resistors
Data line and V
BUS
pulsing session request methods
Integrated V
BUS
voltage comparators
Integrated cable (ID) detector
Highly optimized ULPI-compliant
60 MHz, 8-bit interface between the core and the transceiver
Supports 60 MHz output clock configuration
Integrated Phase-Locked Loop (PLL) supporting one crystal or clock frequency:
19.2 MHz (ISP1507ABS) and 26 MHz (ISP1507BBS)
Fully programmable ULPI-compliant register set
Internal Power-On Reset (POR) circuit
Flexible system integration and very low current consumption, optimized for portable
devices
Power-supply input range is 3.0 V to 3.6 V
Internal voltage regulator supplies 3.3 V and 1.8 V
Charge pump regulator outputs 4.75 V to 5.25 V at a current of up to 50 mA,
tunable using an external capacitor
Supports external V
BUS
charge pump or 5 V V
BUS
switch:
External V
BUS
source is controlled using the PSW_N pin; open-drain PSW_N
allows per-port or ganged power control
Digital FAULT input to monitor the external V
BUS
supply status
Pin CHIP_SELECT_N 3-states the ULPI interface, allowing bus reuse for other
applications
Supports wide range interfacing I/O voltage of 1.65 V to 3.6 V; separate I/O voltage
pins minimize crosstalk
Typical operating current of 10 mA to 48 mA, depending on the USB speed and
bus utilization; not including the charge pump
Typical suspend current of 35
μA
Full industrial grade operating temperature range from
−40 °C
to +85
°C
4 kV ElectroStatic Discharge (ESD) protection at pins DP, DM, ID, V
BUS
and GND
Available in a small HVQFN32 (5 mm
×
5 mm) Restriction of Hazardous Substances
(RoHS) compliant, halogen-free and lead-free package
3. Applications
Digital still camera
Digital TV
Digital Video Disc (DVD) recorder
External storage device, for example:
Magneto-Optical (MO) drive
Optical drive: CD-ROM, CD-RW, DVD
Zip drive
Mobile phone
MP3 player
ISP1507A_ISP1507B_2
© ST-NXP Wireless 2009. All rights reserved.
Product data sheet
Rev. 02 — 19 January 2009
2 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
PDA
Printer
Scanner
Set-Top Box (STB)
Video camera
4. Ordering information
Table 1.
Part
Type number
Marking
Ordering information
Package
Crystal or Name
clock
frequency
19.2 MHz
26 MHz
HVQFN32
HVQFN32
Description
Version
ISP1507ABS
ISP1507BBS
507A
[1]
507B
[1]
plastic thermal enhanced very thin quad flat package;
no leads; 32 terminals; body 5
×
5
×
0.85 mm
plastic thermal enhanced very thin quad flat package;
no leads; 32 terminals; body 5
×
5
×
0.85 mm
SOT617-1
SOT617-1
[1]
The package marking is the first line of text on the IC package and can be used for IC identification.
ISP1507A_ISP1507B_2
© ST-NXP Wireless 2009. All rights reserved.
Product data sheet
Rev. 02 — 19 January 2009
3 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
5. Block diagram
CLOCK
27
USB DATA
SERIALIZER
8
1, 23 to 26,
28, 31, 32
ULPI
INTERFACE
CONTROLLER
19
20
21
REGISTER
MAP
29
17
V
BUS
COMPARATORS
GLOBAL
RESET
13
SRP CHARGE
AND DISCHARGE
RESISTORS
V
BUS
HI-SPEED USB ATX
5
DP
ULPI
INTERFACE
DATA
[7:0]
DIR
STP
NXT
USB DATA
DESERIALIZER
DRV V
BUS
V
BUS
VALID
EXTERNAL
DRV V
BUS
EXTERNAL
TERMINATION
RESISTORS
4
DM
ON-THE-GO MODULE
ID
DETECTOR
7
USB
CABLE
CHIP_SELECT_N
RESET_N
ID
POWER-ON
RESET
GLOBAL
CLOCKS
XTAL1
XTAL2
15
16
PLL
CRYSTAL
OSCILLATOR
5 V CHARGE
PUMP SUPPLY
10
9
8
C_A
C_B
CPGND
V
CC(I/O)
2, 22, 30 interface voltage
internal power
ISP1507
6
12
FAULT
PSW_N
REG3V3
REG1V8
V
CC
14
18
BAND GAP
REFERENCE
VOLTAGE
11
VOLTAGE
REGULATOR
V
REF
3
RREF
004aab035
Fig 1.
Block diagram
ISP1507A_ISP1507B_2
© ST-NXP Wireless 2009. All rights reserved.
Product data sheet
Rev. 02 — 19 January 2009
4 of 81
stm32/stm8
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