HD74AC74
Dual D-Type Positive Edge-Triggered Flip-Flop
ADE-205-361 (Z)
1st. Edition
Sep. 2000
Description
The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q,
Q)
outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse.
Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time
of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input
is locked out and information present will not be transferred to the outputs until the next rising edge of the
Clock Pulse input.
Features
Asynchronous Inputs:
Low input to
S
D
(Set) sets Q to High level
Low input to
C
D
(Clear) sets Q to Low level
Clear and Set are independent of clock
Simultaneous Low on
C
D
and
S
D
makes both Q and
Q
High
•
Outputs Source/Sink 24 mA
HD74AC74
Pin Arrangement
C
D1
1
D
1
2
CP
1
3
S
D1
4
Q
1
5
Q
1
6
GND 7
(Top view)
D
2
C
D2
CP
2
S
D2
CP
1
D
1
S
D1
C
D1
14 V
CC
13
C
D2
12 D
2
11 CP
2
10
S
D2
9 Q
2
8
Q
2
Q
1
Q
1
Q
2
Q
2
Logic Symbol
S
D1
D
1
CP
1
Q
1
Q
1
D
2
S
D2
Q
2
CP
2
Q
2
C
D1
C
D2
Pin Names
D
1
, D
2
CP
1
, CP
2
C
D1
,
C
D2
S
D1
,
S
D2
Q
1
,
Q
1
, Q
2
,
Q
2
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
2
HD74AC74
Truth Table
(Each Half)
Inputs
S
D
L
H
L
H
H
H
H
L
X
:
:
:
:
Q
0
(Q
0
) :
C
D
H
L
L
H
H
H
High Voltage Level
Low Voltage Level
Immaterial
Low-to-High Clock Transition
Previous Q (Q) before Low-to-High Transition of Clock
L
CP
X
X
X
D
X
X
X
H
L
X
Outputs
Q
H
L
H
H
L
Q
0
Q
L
H
H
L
H
Q
0
Logic Diagram
S
D
D
CP
Q
Q
C
D
Please note that this diagram is provised only for the understanding of logic operations and should not be
used to estimate propagation delays.
DC Characteristics
(unless otherwise specified)
Item
Maximum quiescent supply current
Maximum quiescent supply current
Symbol
I
CC
I
CC
Max
40
4.0
Unit
µA
µA
Condition
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = Worst case
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = 25°C
3
HD74AC74
AC Characteristics
Ta = +25°C
C
L
= 50 pF
Item
Maximum clock
frequency
Propagation delay
C
Dn
or
S
Dn
to Q
n
or
Q
n
Propagation delay
C
Dn
or
S
Dn
to Q
n
or
Q
n
Propagation delay
CP
n
to Q
n
or
Q
n
Propagation delay
CP
n
to Q
n
or
Q
n
Note:
t
PHL
t
PLH
t
PHL
t
PLH
Symbol
f
max
V
CC
(V)*
1
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Min
100
140
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Typ
125
160
8.0
6.0
10.5
8.0
8.0
6.0
8.0
6.0
Max
—
—
12.0
9.0
12.0
9.5
13.5
10.0
14.0
10.0
Ta = –40°C to +85°C
C
L
= 50 pF
Min
95
125
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
—
—
13.0
10.0
13.5
10.5
16.0
10.5
14.5
10.5
ns
ns
ns
ns
Unit
MHz
1. Voltage Range 3.3 is 3.3 V
±
0.3 V
Voltage Range 5.0 is 5.0 V
±
0.5 V
AC Operating Requirements: HD74AC74
Ta = +25°C
C
L
= 50 pF
Item
Set-up time, HIGH or LOW
D
n
to CP
n
Hold time, HIGH or LOW
D
n
to CP
n
CP
n
or
C
Dn
or
S
Dn
Pulse width
Recovery time
C
Dn
or
S
Dn
to CP
Note:
t
rec
t
w
t
h
Symbol
t
su
V
CC
(V)*
1
Typ
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
1.5
1.0
–2.0
–1.5
3.0
2.5
–2.5
–2.0
Ta = –40°C
to +85°C
C
L
= 50 pF
Guaranteed Minimum
4.0
3.0
0
0
5.5
4.5
0
0
4.5
3.0
0
0
7.0
5.0
0
0
ns
ns
ns
Unit
ns
1. Voltage Range 3.3 is 3.3 V
±
0.3 V
Voltage Range 5.0 is 5.0 V
±
0.5 V
4
HD74AC74
Capacitance
Item
Input capacitance
Power dissipation capacitance
Symbol
C
IN
C
PD
Typ
4.5
35.0
Unit
pF
pF
Condition
V
CC
= 5.5 V
V
CC
= 5.0 V
5