PRELIMINARY
Delta39K™ ISR™
CPLD Family
CPLDs at FPGA Densities™
Features
•High density
— 15K to 350K usable gates
— 256 to 5376 macrocells
— 92 to 520 maximum I/O pins
— 12 Dedicated Inputs including 4 clock pins, 4 global
control signal pins and 4 JTAG interface pins for
reconfigurability
•Embedded Memory
— 40K to 840K bits embedded SRAM
• 32K to 672K bits of (single port) Cluster memory
• 8K to 168K bits of (dual port) Channel memory
•High speed - 250-MHz in-system operation
•AnyVolt™ interface
— 3.3V, 2.5V and 1.8V V
CC
versions available
— 3.3V, 2.5V and 1.8V I/O capability on all versions
• Low Power Operation
—
0.18-µm 6-layer metal SRAM-based logic process
— Full-CMOS implementation of product term array
—
Standby current as low as 100
µA
at 1.8V V
CC
•Simple timing model
— No penalty for using full 16 product terms / macrocell
— No delay for single product term steering or sharing
•Flexible clocking
— 4 synchronous clocks per device
— 1 spread-aware PLL drives all 4 clock networks
— Locally generated Product Term clock
— Clock polarity control at each register
•Carry-chain logic for fast and efficient arithmetic opera-
tions
•Multiple I/O standards supported
— LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2
(I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+
•Compatible with NOBL™, ZBT™, and QDR™ SRAMs
•Programmable slew rate control on each I/O pin
•User-Programmable Bus Hold capability on each I/O pin
•Fully PCI compliant (to 66 MHz 64-bit PCI spec rev2.2)
•Compact PCI hot swap compatible
•Multiple package/pinout offering across all densities
— 144 to 676 pins in PQFP, BGA and FBGA packages
— Same pinout for 3.3V/2.5V and 1.8V devices
— Simplifies design migration across density
— Self-Boot™ solution in BGA and FBGA packages
•In-System Reprogrammable™ (ISR™)
— JTAG-compliant on-board programming
— Design changes don’t cause pinout changes
•IEEE1149.1 JTAG boundary scan
Development Software
•Warp™
— IEEE 1076/1164 VHDL or IEEE 1364 Verilog context
sensitive editing.
— Active-HDL FSM graphical finite state machine editor
— Active-HDL SIM post-synthesis timing simulator
— Architecture Explorer for detailed design analysis
— Static Timing Analyzer for critical path analysis
— Available on Windows 95, 98 & NT for $99
— Supports all Cypress Programmable Logic Products
Delta39K™ ISR CPLD Family Members
Typical
Gates
[1]
8K–24K
16K–48K
23K–72K
46K–144K
77K–241K
92K–288K
115K–361K
161K–505K
Cluster
memory
(Kbits)
32
64
96
192
320
384
480
672
Channel
memory
(Kbits)
8
16
24
48
80
96
120
168
Maximum
I/O Pins
134
176
218
302
386
428
470
520
f
MAX2
(MHz)
256
238
238
222
181
181
167
154
Speed - t
PD
Pin-to-Pin
(ns)
6.5
7.0
7.0
7.5
8.5
8.5
8.5
9.0
Standby I
CC
[2]
T
A
=25°C
3.3/2.5V
10 mA
10 mA
10 mA
10 mA
10 mA
10 mA
10 mA
10 mA
1.8V
100
µA
200
µA
300
µA
600
µA
1250
µA
1250
µA
1500
µA
2100
µA
Device
39K15
39K30
39K50
39K100
39K165
39K200
39K250
39K350
Macrocells
256
512
768
1536
2560
3072
3840
5376
Note:
1. Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used.
2. Standby I
CC
values are with PLL not utilized, no output load and stable inputs
Cypress Semiconductor Corporation
Document #: 38-03039 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134
• 408-943-2600
Revised April 4, 2001
PRELIMINARY
Delta39K Speed Bins
[3]
Device
39K15
39K30
39K50
39K100
39K165
39K200
39K250
39K350
250
X
X
X
X
X
X
X
X
222
200
181
167
154
Delta39K™ ISR™
CPLD Family
125
X
X
X
X
X
X
X
X
83
X
X
X
X
X
X
X
X
Device Package Offering and I/O Count Including Dedicated Clock and Control Inputs
Self-Boot Solution
[4]
208-EQFP 144-FBGA 256-FBGA 484-FBGA 676-FBGA
Device
39K15
39K30
39K50
39K100
39K165
39K200
39K250
39K350
28X28 mm
0.5-mm
pitch
13x13 mm
1.0-mm
pitch
17x17 mm
1.0-mm
pitch
23x23 mm
1.0-mm
pitch
27x27 mm
1.0-mm
pitch
256-FBGA
17x17 mm
1.0-mm
pitch
388-BGA
35x35 mm
1.27-mm
pitch
484-FBGA
23x23 mm
1.0-mm pitch
676-FBGA
27x27 mm
1.0-mm
pitch
134
136
136
136
136
136
136
136
92
92
134
176
180
180
302
356
368
470
520
134
176
218
294
294
294
294
294
218
302
386
428
470
520
Notes:
3. Speed bins shown here are for Commercial operating range. Please refer to Delta39K Ordering Information on page 41 for Industrial range speed bins.
4. Self-Boot Solution integrates the boot PROM (Flash Memory) with Delta39K die inside the same package.
Document #: 38-03039 Rev. **
Page 2 of 57
PRELIMINARY
Delta39K™ ISR™
CPLD Family
GCLK[3:0]
PLL & Clock MUX
GCTL[3:0]
4
4
GCLK[3:0]
4
I/O Bank 7
4
4
I/O Bank 6
4
LB 0
LB 1
LB 2
LB 3
Cluster
RAM
LB 7
LB 6
LB 0
LB 1
LB 7
LB 6
LB 0
LB 1
LB 7
LB 6
LB 0
LB 1
LB 7
LB 6
PIM
LB 5
LB 4
Cluster
RAM
Channel
RAM
LB 2
LB 3
Cluster
RAM
PIM
LB 5
LB 4
Cluster
RAM
Channel
RAM
LB 2
LB 3
Cluster
RAM
PIM
LB 5
LB 4
Cluster
RAM
Channel
RAM
LB 2
LB 3
Cluster
RAM
PIM
LB 5
LB 4
Cluster
RAM
Channel
RAM
GCLK[3:0]
4
4
4
4
I/O Bank 0
LB 0
LB 1
LB 2
LB 3
Cluster
RAM
LB 7
LB 6
LB 0
LB 1
LB 7
LB 6
LB 0
LB 1
LB 7
LB 6
LB 0
LB 1
LB 7
LB 6
PIM
LB 5
LB 4
Cluster
RAM
Channel
RAM
LB 2
LB 3
Cluster
RAM
PIM
LB 5
LB 4
Cluster
RAM
Channel
RAM
LB 2
LB 3
Cluster
RAM
PIM
LB 5
LB 4
Cluster
RAM
Channel
RAM
LB 2
LB 3
Cluster
RAM
PIM
LB 5
LB 4
Cluster
RAM
Channel
RAM
GCLK[3:0]
4
4
4
4
I/O Bank 1
LB 0
LB 1
LB 2
LB 3
Cluster
RAM
LB 7
LB 6
LB 0
LB 1
LB 7
LB 6
LB 0
LB 1
LB 7
LB 6
LB 0
LB 1
LB 7
LB 6
PIM
LB 5
LB 4
Cluster
RAM
Channel
RAM
LB 2
LB 3
Cluster
RAM
PIM
LB 5
LB 4
Cluster
RAM
Channel
RAM
LB 2
LB 3
Cluster
RAM
PIM
LB 5
LB 4
Cluster
RAM
Channel
RAM
LB 2
LB 3
Cluster
RAM
PIM
LB 5
LB 4
Cluster
RAM
Channel
RAM
I/O Bank 2
I/O Bank 3
Figure 1. Delta39K100 Block Diagram (3 Rows x 4 Columns) with I/O Bank Structure
Document #: 38-03039 Rev. **
Page 3 of 57
I/O Bank 4
I/O Bank 5
PRELIMINARY
General Description
The Delta39K family, based on a 0.18
µm,
6-layer metal
CMOS logic process, offers a wide range of high-density solu-
tions at unparalleled system performance. The Delta39K fam-
ily is designed to combine the high speed, predictable timing,
and ease of use of CPLDs with the high densities and low
power of FPGAs. With devices ranging from 15,000 to 350,000
usable gates, the family features devices ten times the size of
previously available CPLDs. Even at these large densities, the
Delta39K family is fast enough to implement a fully synthesiz-
able 64-bit, 66-MHz PCI core.
The architecture is based on Logic Block Clusters (LBC) that
are connected by Horizontal and Vertical (H&V) routing chan-
nels. Each LBC features eight individual Logic Blocks (LB) and
two cluster memory blocks. Adjacent to each LBC is a channel
memory block, which can be accessed directly from the I/O
pins. Both types of memory blocks are highly configurable and
can be cascaded in width and depth. See
Figure 1
for a block
diagram of the Delta39K architecture.
All the members of the Delta39K family have Cypress’s highly
regarded In-System Reprogrammability (ISR) feature, which
simplifies both design and manufacturing flows, thereby re-
ducing costs. The ISR feature provides the ability to reconfig-
ure the devices without having design changes cause pinout
or timing changes in most cases. The Cypress ISR function is
implemented through a JTAG-compliant serial interface. Data
is shifted in and out through the TDI and TDO pins respective-
ly. Superior routability, simple timing, and the ISR allows users
to change existing logic designs while simultaneously fixing
pinout assignments and maintaining system performance.
The entire family features JTAG for ISR and boundary scan,
and is compatible with the PCI Local Bus specification, meet-
ing the electrical and timing requirements. The Delta39K fam-
ily also features user programmable bus-hold and slew rate
control capabilities on each I/O pin.
AnyVolt Interface
All Delta39KV devices feature an on-chip regulator, which ac-
cepts 3.3V or 2.5V on the V
CC
supply pins and steps it down
to 1.8V internally, the voltage level at which the core operates.
I/O Block
Delta39K™ ISR™
CPLD Family
The Delta39KZ devices accept 1.8V on the V
CC
supply pins
directly. With Delta39K’s AnyVolt technology, the I/O pins can
be connected to either 1.8V, 2.5V, or 3.3V. All Delta39K devic-
es are 3.3V tolerant regardless of V
CCIO
or V
CC
settings.
Device
39KV
39KZ
V
CC
3.3V or 2.5V
1.8V
V
CCIO
3.3V or 2.5V or 1.8V or 1.5V
[5]
3.3V or 2.5V or 1.8V or 1.5V
[5]
Global Routing Description
The routing architecture of the Delta39K is made up of hori-
zontal and vertical (H&V) routing channels. These routing
channels allow signals from each of the Delta39K architectural
components to communicate with one another. In addition to
the horizontal and vertical routing channels that interconnect
the I/O banks, channel memory blocks, and logic block clus-
ters, each LBC contains a Programmable Interconnect Matrix
(PIM™), which is used to route signals among the logic blocks
and the cluster memory blocks.
Figure 2
is a block diagram of the routing channels that inter-
face within the Delta39K architecture. The LBC is exactly the
same for every member of the Delta39K CPLD family.
Logic Block Cluster (LBC)
The Delta39K architecture consists of several logic block clus-
ters, each of which have 8 Logic Blocks (LB) and 2 cluster
memory blocks connected via a Programmable Interconnect
Matrix (PIM) as shown in
Figure 3.
Each cluster memory block
consists of 8-Kbit single-port RAM, which is configurable as
synchronous or asynchronous. The cluster memory blocks
can be cascaded with other cluster memory blocks within the
same LBC as well as other LBCs to implement larger memory
functions. If a cluster memory block is not specifically utilized
by the designer, Cypress’s
Warp
software can automatically
use it to implement large blocks of logic.
All LBCs interface with each other via horizontal and vertical
routing channels.
LB
LB
LB
LB
Cluster
Memory
Block
LB
72
LB
Cluster
PIM
64
LB
LB
Cluster
Memory
Block
Channel
Memory
Block
Channel memory
outputs drive
dedicated tracks in the
horizontal and vertical
routing channels
72
I/O Block
64
H-to-V
PIM
V-to-H
PIM
Pin inputs from the I/O cells
drive dedicated tracks in the
horizontal and vertical routing
channels
Figure 2. Delta39K Routing Interface
Note:
5. For HSTL only.
Document #: 38-03039 Rev. **
Page 4 of 57
PRELIMINARY
Delta39K™ ISR™
CPLD Family
Clock Inputs
GCLK[3:0]
4
Logic
Block
0
CC
36
16
36
16
Logic
Block
7
CC
Logic
Block
1
CC
36
16
36
16
Logic
Block
6
CC
Logic
Block
2
CC
36
16
PIM
36
16
Logic
Block
5
CC
Logic
Block
3
36
16
36
16
Logic
Block
4
Cluster
Memory
0
25
8
25
8
Cluster
Memory
1
CC = Carry Chain
64 Inputs From
Horizontal Routing
Channel
64 Inputs From
Vertical Routing
Channel
144 Outputs to
Horizontal and Vertical
cluster-to-channel PIMs
Figure 3. Delta39K Logic Block Cluster Diagram
Logic Block (LB)
The logic block is the basic building block of the Delta39K ar-
chitecture. It consists of a product term array, an intelligent
product-term allocator, and 16 macrocells.
Product Term Array
Each logic block features a 72 x 83 programmable product
term array. This array accepts 36 inputs from the PIM. These
inputs originate from device pins and macrocell feedbacks as
well as cluster memory and channel memory feedbacks. Ac-
tive LOW and active HIGH versions of each of these inputs are
generated to create the full 72-input field. The 83 product
terms in the array can be created from any of the 72 inputs.
Of the 83 product terms, 80 are for general-purpose use for
the 16 macrocells in the logic block. Two of the remaining three
product terms in the logic block are used as asynchronous set
and asynchronous reset product terms. The final product term
is the Product Term clock (PTCLK) and is shared by all 16
macrocells within a logic block.
Product Term Allocator
Through the product term allocator,
Warp
software automati-
cally distributes the 80 product terms as needed among the 16
macrocells in the logic block. The product term allocator pro-
vides two important capabilities without affecting performance:
product term steering and product term sharing.
Product Term Steering
Product term steering is the process of assigning product
terms to macrocells as needed. For example, if one macrocell
requires ten product terms while another needs just three, the
product term allocator will “steer” ten product terms to one
macrocell and three to the other. On Delta39K devices, prod-
uct terms are steered on an individual basis. Any number be-
tween 1and 16 product terms can be steered to any macrocell.
Product Term Sharing
Product term sharing is the process of using the same product
term among multiple macrocells. For example, if more than
one function has one or more product terms in its equation that
are common to other functions, those product terms are only
programmed once. The Delta39K product term allocator al-
lows sharing across groups of four macrocells in a variable
fashion. The software automatically takes advantage of this
capability so that the user does not have to intervene.
Note that neither product term sharing nor product term steer-
ing have any effect on the speed of the product. All steering
and sharing configurations have been incorporated in the tim-
ing specifications for the Delta39K devices.
.
Document #: 38-03039 Rev. **
Page 5 of 57
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