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74HC08
Quad 2−Input AND Gate
High−Performance Silicon−Gate CMOS
The 74HC08 is identical in pinout to the LS08. The device inputs are
compatible with Standard CMOS outputs; with pullup resistors, they
are compatible with LSTTL outputs.
Features
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MARKING
DIAGRAMS
14
14
1
SOIC−14
D SUFFIX
CASE 751A
1
HC08G
AWLYWW
•
•
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
ESD Performance: HBM
>
2000 V; Machine Model
>
200 V
Chip Complexity: 24 FETs or 6 Equivalent Gates
These are Pb−Free Devices
LOGIC DIAGRAM
A1
B1
A2
B2
A3
B3
A4
B4
1
2
4
5
9
10
12
13
PIN 14 = V
CC
PIN 7 = GND
3
Y1
14
14
1
TSSOP−14
DT SUFFIX
CASE 948G
1
HC
08
ALYW
G
G
6
Y2
Y = AB
8
Y3
HC08
= Device Code
A
= Assembly Location
WL or L = Wafer Lot
Y
= Year
WW or W = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
11
Y4
FUNCTION TABLE
Inputs
A
L
L
H
H
B
L
H
L
H
Output
Y
L
L
L
H
Pinout: 14−Lead Packages
(Top View)
V
CC
14
B4
13
A4
12
Y4
11
B3
10
A3
9
Y3
8
ORDERING INFORMATION
1
A1
2
B1
3
Y1
4
A2
5
B2
6
Y2
7
GND
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2007
March, 2007
−
Rev. 1
1
Publication Order Number:
74HC08/D
74HC08
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS
Symbol
V
CC
V
in
I
in
I
out
I
CC
P
D
T
stg
T
L
V
out
Parameter
Value
Unit
V
V
V
mA
mA
mA
mW
_C
_C
260
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
– 0.5 to + 7.0
– 0.5 to V
CC
+ 0.5
– 0.5 to V
CC
+ 0.5
±20
±25
±50
500
450
– 65 to + 150
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air,
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package
SOIC Package†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package:
−
6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to
GND)
Operating Temperature Range, All Package Types
Input Rise/Fall Time
(Figure 1)
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Min
2.0
0
– 55
0
0
0
Max
6.0
V
CC
+ 125
1000
500
400
Unit
V
V
_C
ns
ORDERING INFORMATION
Device
74HC08DR2G
74HC08DTR2G
Package
SOIC−14
(Pb−Free)
TSSOP−14*
Shipping
†
2500/Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
74HC08
DC CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
V
IH
Parameter
Minimum High−Level Input Voltage
Condition
V
out
= 0.1V or V
CC
−0.1V
|I
out
|
≤
20mA
V
CC
(V)
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
≤
2.4mA
|I
out
|
≤
4.0mA
|I
out
|
≤
5.2mA
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
≤
2.4mA
|I
out
|
≤
4.0mA
|I
out
|
≤
5.2mA
3.0
4.5
6.0
6.0
6.0
Guaranteed Limit
−55
to 25°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
±0.1
2.0
≤85°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
±1.0
20
≤125°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.20
3.70
5.20
0.1
0.1
0.1
0.40
0.40
0.40
±1.0
40
mA
mA
V
Unit
V
V
IL
Maximum Low−Level Input Voltage
V
out
= 0.1V or V
CC
−
0.1V
|I
out
|
≤
20mA
V
V
OH
Minimum High−Level Output Voltage
V
in
= V
IH
or V
IL
|I
out
|
≤
20mA
V
in
=V
IH
or V
IL
V
V
OL
Maximum Low−Level Output Voltage
V
in
= V
IH
or V
IL
|I
out
|
≤
20mA
V
in
= V
IH
or V
IL
I
in
I
CC
Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS
(C
L
= 50pF, Input t
r
= t
f
= 6ns)
Symbol
t
PLH
,
t
PHL
Parameter
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
V
CC
(V)
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Guaranteed Limit
−55
to 25°C
75
30
15
13
75
27
15
13
10
≤85°C
95
40
19
16
95
32
19
16
10
≤125°C
110
55
22
19
110
36
22
19
10
Unit
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
ns
C
in
Maximum Input Capacitance
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
CC
= 5.0 V, V
EE
= 0 V
C
PD
Power Dissipation Capacitance (Per Buffer)*
20
pF
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
. For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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3
74HC08
t
r
INPUT
A OR B
t
PLH
90%
OUTPUT Y
t
TLH
50%
10%
t
THL
90%
50%
10%
t
PHL
t
f
V
CC
GND
Figure 1. Switching Waveforms
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
C
L
*
*Includes all probe and jig capacitance
Figure 2. Test Circuit
A
B
Y
Figure 3. Expanded Logic Diagram
(1/4 of the Device)
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