HUF76131SK8
Data Sheet
January 2003
10A, 30V, 0.013 Ohm, N-Channel, Logic
Level UltraFET Power MOSFET
This N-Channel power MOSFET is
®
manufactured using the innovative
UltraFET process. This advanced
process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
Formerly developmental type TA76131.
Features
• Logic Level Gate Drive
• 10A, 30V
• Ultra Low On-Resistance, r
DS(ON)
= 0.013Ω
• Temperature Compensating PSPICE
®
Model
• Thermal Impedance SPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
SOURCE(1)
DRAIN(8)
Ordering Information
PART NUMBER
HUF76131SK8
PACKAGE
MS-012AA
BRAND
76131SK8
SOURCE(2)
DRAIN(7)
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76131SK8T.
SOURCE(3)
DRAIN(6)
GATE(4)
DRAIN(5)
Packaging
JEDEC MS-012AA
BRANDING DASH
5
1
2
3
4
©2003 Fairchild Semiconductor Corporation
HUF76131SK8 Rev. B1
HUF76131SK8
Absolute Maximum Ratings
T
A
= 25
o
C, Unless Otherwise Specified
HUF76131SK8
30
30
±20
10
Figure 5
Figure 6
2.5
0.02
-55 to 150
300
260
UNITS
V
V
V
A
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
Drain to Gate Voltage (R
GS
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Drain Current
Continuous (Figure 2) (Notes 2, 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
pkg
W
W/
o
C
o
C
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 150
o
C.
Electrical Specifications
PARAMETER
T
A
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
I
DSS
I
GSS
r
DS(ON)
TEST CONDITIONS
I
D
= 250µA, V
GS
= 0V (Figure 11)
V
GS
= V
DS
, I
D
= 250µA (Figure 10)
V
DS
= 25V, V
GS
= 0V
V
DS
= 25V, V
GS
= 0V, T
A
= 150
o
C
V
GS
=
±20V
I
D
= 10A, V
GS
= 4.5V (Figures 9,14)
I
D
= 10A, V
GS
= 5V
I
D
= 10A, V
GS
= 10V
MIN
30
1
-
-
-
-
-
-
-
-
-
-
-
-
V
GS
= 0V to 10V V
DD
= 15V, I
D
≅
10A,
V
GS
= 0V to 5V R
L
= 1.5Ω, I
g(REF)
= 1.0mA
(Figure 13)
V
GS
= 0V to 1V
-
-
-
-
-
V
DS
= 25V, V
GS
= 0V, f = 1MHz
(Figure 12)
Pad Area = 0.76 in
2
(Note 2)
Pad Area = 0.054 in
2
(See TB377)
Pad Area = 0.0115 in
2
(See TB377)
-
-
-
-
-
-
TYP
-
-
-
-
-
0.017
0.015
0.011
-
15
61
33
36
-
39
22
1.53
4.00
9.50
1605
685
115
-
-
-
MAX
-
-
1
250
±100
0.018
0.017
0.013
115
-
-
-
-
105
47
26
1.85
-
-
-
-
-
50
143.4
177.3
UNITS
V
V
µA
µA
nA
Ω
Ω
Ω
ns
ns
ns
ns
ns
ns
nC
nC
nC
nC
nC
pF
pF
pF
o
C/W
o
C/W
o
C/W
Drain to Source Breakdown Voltage
Gate to Source Threshold Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On Resistance
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
Total Gate Charge
Gate Charge at 5V
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Thermal Resistance Junction to Ambient
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
Q
g(TOT)
Q
g(5)
Q
g(TH)
Q
gs
Q
gd
C
ISS
C
OSS
C
RSS
R
θJA
V
DD
= 15V, I
D
≅
10A, R
L
= 1.5Ω, V
GS
=
5V,
R
GS
= 6.8Ω
(Figure 15)
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
NOTES:
2. 50
o
C/W measured using FR-4 board with 0.76 in
2
footprint at 10 seconds.
3. 177.3
o
C/W measured using FR-4 board with 0.0115 in
2
footprint at 1000 seconds.
©2003 Fairchild Semiconductor Corporation
HUF76131SK8 Rev. B1
SYMBOL
V
SD
t
rr
Q
RR
I
SD
= 10A
I
SD
= 2.3A
TEST CONDITIONS
MIN
-
-
-
-
TYP
-
-
-
-
MAX
1.25
1.1
57
81
UNITS
V
V
ns
nC
I
SD
= 2.3A, dI
SD
/dt = 100A/µs
I
SD
= 2.3A, dI
SD
/dt = 100A/µs
HUF76131SK8
Typical Performance Curves
1.2
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
150
T
A
, AMBIENT TEMPERATURE (
o
C)
I
D
, DRAIN CURRENT (A)
12
10
8
6
4
2
0
25
50
75
100
125
150
T
A
, AMBIENT TEMPERATURE (
o
C)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
10
THERMAL IMPEDANCE
Z
θ
JA
, NORMALIZED
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
0.01
t
2
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θ
JA
x R
θ
JA
+ T
A
10
-2
10
-1
10
0
10
1
10
2
10
3
SINGLE PULSE
0.001
10
-5
10
-4
10
-3
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
T
J
= MAX RATED
T
A
= 25
o
C
1000
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
100
100µs
I
DM
, PEAK CURRENT (A)
I
D
, DRAIN CURRENT (A)
100
V
GS
= 5V
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
1ms
10
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
I = I
25
150 - T
A
125
T
A
= 25
o
C
10
0
10
1
10ms
V
DSS(MAX)
= 30V
1
1
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
100
1
10
-5
10
-4
10
-3
10
-2
10
-1
t, PULSE WIDTH (s)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
©2003 Fairchild Semiconductor Corporation
HUF76131SK8 Rev. B1
HUF76131SK8
Typical Performance Curves
100
I
AS
, AVALANCHE CURRENT (A)
If R = 0
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R
≠
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
I
D
, DRAIN CURRENT (A)
(Continued)
50
V
GS
= 10V
V
GS
= 5V
V
GS
= 4.5V
V
GS
= 4V
V
GS
= 3.5V
40
10
STARTING T
J
= 150
o
C
STARTING T
J
= 25
o
C
30
20
V
GS
= 3V
10
1
0.1
1
10
100
0
0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T
A
= 25
o
C
0.5
1.0
1.5
2.0
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
2.5
t
AV
, TIME IN AVALANCHE (ms)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
50
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
I
D
, DRAIN CURRENT (A)
40
FIGURE 7. SATURATION CHARACTERISTICS
1.75
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
GS
= 10V, I
D
= 10A
1.5
30
1.25
20
1.0
10
150
o
C
25
o
C
-55
o
C
V
DD
= 15V
3.5
4.0
0
0
0.5
2.0
2.5
3.0
1.0
1.5
V
GS
, GATE TO SOURCE VOLTAGE (V)
0.75
-80
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
V
GS
= V
DS
, I
D
= 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.2
I
D
= 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
1.0
1.1
0.8
1.0
0.6
0.9
0.4
-80
-40
0
40
80
120
o
C)
T
J
, JUNCTION TEMPERATURE (
160
0.8
-80
-40
0
40
80
120
o
C)
T
J
, JUNCTION TEMPERATURE (
160
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
©2003 Fairchild Semiconductor Corporation
HUF76131SK8 Rev. B1
HUF76131SK8
Typical Performance Curves
2500
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
= C
DS
+ C
GD
(Continued)
10
2000
C, CAPACITANCE (pF)
C
ISS
1500
8
6
1000
C
OSS
500
C
RSS
0
0
5
10
15
20
25
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
30
4
2
V
DD
= 15V
0
0
10
WAVEFORMS IN
DESCENDING ORDER:
I
D
= 20A
I
D
= 10A
I
D
= 5A
I
D
= 2.5A
40
50
20
30
Q
g
, GATE CHARGE (nC)
NOTE: Refer to Fairchild Application Notes 7254 and 7260.
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
80
r
DS(ON)
, ON-STATE RESISTANCE (mΩ)
200
V
DD
= 15V, I
D
= 10A, R
L
= 1.5Ω
60
I
D
= 5A
SWITCHING TIME (ns)
I
D
= 10A
I
D
= 20A
150
t
r
t
d(OFF)
100
t
f
40
I
D
= 2.5A
20
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
0
2
6
8
4
V
GS
, GATE TO SOURCE VOLTAGE (V)
10
50
t
d(ON)
0
0
10
20
30
40
R
GS
, GATE TO SOURCE RESISTANCE (Ω)
50
FIGURE 14. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
V
DS
BV
DSS
L
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
V
GS
DUT
t
P
R
G
I
AS
V
DD
-
t
P
V
DS
V
DD
+
0V
I
AS
0.01Ω
0
t
AV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
©2003 Fairchild Semiconductor Corporation
HUF76131SK8 Rev. B1
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