HSP48410
Data Sheet
May 1999
File Number
3185.2
Histogrammer/Accumulating Buffer
The Intersil HSP48410 is an 84 lead Histogrammer IC
intended for use in image and signal analysis. The on-board
memory is configured as 1024 x 24 array. This translates to
a pixel resolution of 10 bits and an image size of 4k x 4k with
no possibility of overflow.
In addition to Histogramming, the HSP48410 can generate
and store the Cumulative Distribution Function for use in
Histogram Equalization applications. Other capabilities of
the HSP48410 include: Bin Accumulation, Look Up Table,
24-bit Delay Memory, and Delay and Subtract mode.
A Flash Clear pin is available in all modes of operation and
performs a single cycle reset on all locations of the internal
memory array and all internal data paths.
The HSP48410 includes a fully asynchronous interface
which provides a means for communications with a host,
such as a microprocessor. The interface includes dedicated
Read/Write pins and an address port which are
asynchronous to the system clock. This allows random
access of the Histogram Memory Array for analysis or
conditioning of the stored data.
Features
• 10-Bit Pixel Data
• 4k x 4k Frame Sizes
• Asynchronous Flash Clear Pin
• Single Cycle Memory Clear
• Fully Asynchronous 16 or 24-Bit Host Interface
• Generates and Stores Cumulative Distribution Function
• Look Up Table Mode
• 1024 x 24-Bit Delay Memory
• 24-Bit Three State I/O Bus
• DC to 40MHz Clock Rate
Applications
• Histogramming
• Histogram Equalization
• Image and Signal Analysis
• Image Enhancement
• RGB Video Delay Line
Ordering Information
PART NUMBER
HSP48410JC-33
HSP48410JC-40
HSP48410GC-33
HSP48410GC-40
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
0 to 70
0 to 70
PACKAGE
84 Ld PLCC
84 Ld PLCC
84 Ld PGA
84 Ld PGA
PKG.
NO.
N84.1.15
N84.1.15
G84.A
G84.A
Block Diagram
24
24
HISTOGRAM
MEMORY
ARRAY
MUX
24
DATA
IN
DATA
OUT
24
ADDER
DIO0-23
DIO
INTERACE
DIN0-23
PIN0-9
10
ADDRESS
GENERATOR
10
ADDRESS
IOADD0-9
10
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
HSP48410
Pin Description
NAME
CLK
PLCC PIN
1
TYPE
I
DESCRIPTION
Clock Input. This input has no effect on the chips functionality when the chip is programmed
to an asynchronous mode. All signals denoted as synchronous have their timing specified
with reference to this signal.
Pixel Input. This input bus is sampled by the rising edge of clock. It provides the on-chip RAM
with address values in Histogram, Bin Accumulate and LUT(write) mode. During Asynchro-
nous modes it is unused.
The Load pin is used to load the FCT0-2 bits into the FCT Registers. (See below).
These three pins are decoded to determine the mode of operation for the chip. The signals
are sampled by the rising edge of LD and take effect after the rising edge of LD. Since the
loading of this function is asynchronous to CLK, it is necessary to disable the START pin dur-
ing loading and enable START at least 1 CLK cycle following the LD pulse.
This pin informs the on-chip circuitry which clock cycle will start and/or stop the current mode
of operation. Thus, the modes are asynchronously selected (via LD) but are synchronously
started and stopped. This input is sampled by the rising edge of CLK. The actual function of
this input depends on the mode that is selected. START must always be held high (disabled)
when changing modes. This will provide a smooth transition from one mode to the next by
allowing the part to reconfigure itself before a new mode begins. When START is high,
LUT(read) mode is enabled except for Delay and Delay and Subtract modes.
Flash Clear. This input provides a fully asynchronous signal which effectively resets all bits
in the RAM Array and the input and output data paths to zero.
Data Input Bus. Provides data to the Histogrammer during Bin Accumulate, LUT, Delay and
Delay and Subtract modes. Synchronous to CLK.
Asynchronous Data Bus. Provides RAM access for a microprocessor in preconditioning the
memory array and reading the results of the previous operation. Configurable as either a 24
or 16-bit bus.
RAM address in asynchronous modes. Sampled on the falling edge of WR or RD.
Upper Word Select. In 16-bit Asynchronous mode, a one on this pin denotes the contents of
DIO0-7 as being the upper eight bits of the data in or out of the Histogrammer. A zero means
that DIO0-15 are the lower 16 bits. In all other modes, this pin has no effect.
Write enable to the RAM for the data on DIO0-23 when the HSP48410 is configured in one
of the asynchronous modes. Asynchronous to CLK.
Read control for the data on DIO0-23 in asynchronous modes. Output enable for DIO0-23
in other modes. Asynchronous to CLK.
+5V. 0.1µF capacitors between the V
CC
and GND pins are recommended.
Ground
PIN0-9
3-11, 83
I
LD
FCT0-2
15
16-18
I
I
START
14
I
FC
12
I
DIN0-23
58-63,
65-82
33-40,
42-57
I
DIO0-23
I/O
IOADD0-9
UWS
22-31
21
I
I
WR
19
I
RD
13
I
V
CC
GND
NOTES:
2, 32
20, 41, 64, 84
1. An overbar denotes an active low signal.
2. Bit 0 is the LSB on all busses.
4
HSP48410
Functional Description
The Histogrammer is intended for use in signal and image
processing applications. The on-board RAM is 24 bits by
1024 locations. For histogramming, this translates to an
image size of 4k x 4k with 10-bit data. A Functional Block
Diagram of the part is shown in Figure 1.
In addition to histogramming, the HSP48410 will also
perform Histogram Accumulation while feeding the results
back into the memory array. The on-board RAM will then
contain the Cumulative Distribution Function and can be
used for further operation such as histogram equalization.
Other modes are: Bin Accumulate, Look Up Table (LUT),
Delay Memory, and Delay and Subtract. The part can also
be accessed as a 24-bit by 1024 word asynchronous RAM
for preconditioning or reading the results of the histogram.
The Histogrammer can be accessed both synchronously
and asynchronously to the system clock (CLK). It was
designed to be configured asynchronously by a
microprocessor, then switched to a synchronous mode to
process data. The result of the processing can then be read
out synchronously, or the part can be switched to one of the
asynchronous modes so the data may be read out by a
microprocessor. All modes are synchronous except for the
Asynchronous 16 and 24 modes.
A Flash Clear operation allows the user to reset the entire
RAM array and all input and output data paths in a single
cycle.
DIO Interface
The DIO Interface Section transfers data between the
Histogrammer and the outside world. In the synchronous
modes, DIO acts as a synchronous output for the data
currently being processed by the chip; RD acts as the output
enable for the DIO bus; WR and IOADD0-9 have no effect.
When either of the Asynchronous modes are selected (16 or
24-bit), the RAM output is passed directly to the DIO bus on
read cycles, and on write cycles, data input on DIO goes to
the RAM input port. In this case, data reads and writes are
controlled by RD, WR and IOADD0-9.
Function Decode
This section provides the signals needed to configure the
part for the different modes. The eight modes are decoded
from FCT0-2 on the rising edge of LD (see Table 1). The
output of this section is a set of signals which control the
path of data through the part.
The mode should only be changed while START is high.
After changing from one mode to another, START must be
clocked high by the rising edge of CLK at least once.
TABLE 1. FUNCTION DECODE
FCT
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
Histogram
Histogram Accumulate
Delay and Subtract
Look Up Table
Bin Accumulate
Delay Memory
Asynchronous 24
Asynchronous 16
MODE
Histogram Memory Array
The Histogram Memory Array is a 24-bit by 1024 deep RAM.
Depending on the current mode, its input data comes from
either the synchronous input DIN0-23, from the
asynchronous data bus DIO0-23, or from the output of the
adder. The output data goes to the DIO bus in both
synchronous and asynchronous modes.
Address Generator
This section of the circuit determines the source of the RAM
address. In the synchronous modes, the address is taken
from either the output of the counter or PIN0-9. The pixel
input bus is used for Histogram, Bin Accumulate, and
LUT(read) modes. All other synchronous modes, i.e.
Histogram Accumulate, LUT(write), Delay, and Delay and
Subtract use the counter output. The counter is reset on the
first rising edge of CLK after a falling edge on START.
During asynchronous modes, the read and write addresses
to the RAM are taken from the IOADD bus on the falling
edge of the RD and WR signals, respectively.
Flash Clear
Flash Clear allows the user to clear the entire RAM with a
single pin. When the FC pin is low, all bits of the RAM and
the data path from the RAM to DIO0-23 are set to zero. The
FC pin is asynchronous with respect to CLK: the reset
begins immediately following a low on this signal. For
synchronous modes, in order to ensure consistent results,
FC should only be active while START is high. For
asynchronous modes, WR must remain inactive while FC
is low.
Adder Input
The Adder Input Control Section contains muxes, registers
and other logic that provide the proper data to the adder. The
configuration of this section is controlled by the output of the
Function Decode Section.
5
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