DATASHEET
CD4015BMS
CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output
FN3295
Rev 0.00
December 1992
Features
• High-Voltage Type (20V Rating)
• Medium Speed Operation 12MHz (typ.) Clock Rate at
VDD - VSS = 10V
• Fully Static Operation
• 8 Master-Slave Flip-Flops Plus Input and Output Buffering
• 100% Tested For Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• Maximum Input Current of 1A at 18V Over Full Pack-
age-Temperature Range; 100nA at 18V and 25
o
C
• Noise Margin (Full Package-Temperature Range) =
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Pinout
CD4015BMS
TOP VIEW
CLOCK B 1
Q4B 2
Q3A 3
Q2A 4
Q1A 5
RESET A 6
DATA A 7
VSS 8
16 VDD
15 DATA B
14 RESET B
13 Q1B
12 Q2B
11 Q3B
10 Q4A
9 CLOCK A
Functional Diagram
VDD
16
DATA A
CLOCK A
RESET A
7
9
6
4
STAGE
5
4
3
10
DATA B
15
1
14
4
STAGE
13
12
11
2
Q1A
Q2A
Q3A
Q4A
Q1B
Q2B
Q3B
Q4B
Applications
• Serial-Input/Parallel-Output Data Queueing
• Serial to Parallel Data Conversion
• General-Purpose Register
Description
CD4015BMS consists of two identical, independent, 4-stage
serial-input/parallel output registers. Each register has inde-
pendent CLOCK and RESET inputs as well as a single serial
DATA input. “Q” outputs are available from each of the four
stages on both registers. All register stages are D type, mas-
ter-slave flip-flops. The logic level present at the DATA input
is transferred into the first register stage and shifted over one
stage at each positive-going clock transition. Resetting of all
stages is accomplished by a high level on the reset line.
Register expansion to 8 stages using one CD4015BMS
package, or to more than 8 stages using additional
CD4015BMS’s is possible.
The CD4015BMS is supplied in these 16 lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4X
H1F
H6W
CLOCK B
RESET B
8
VSS
FN3295 Rev 0.00
December 1992
Page 1 of 8
CD4015BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input
10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265
o
C
At Distance 1/16 1/32 Inch (1.59mm
0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
ja
jc
o
C/W
o
C/W
Ceramic DIP and FRIT Package . . . . . 80
20
Flatpack Package . . . . . . . . . . . . . . . . 70
o
C/W
20
o
C/W
Maximum Package Power Dissipation (PD) at +125
o
C
For TA = -55
o
C to +100
o
C (Package Type D, F, K) . . . . . . 500mW
For TA = +100
o
C to +125
o
C (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/
o
C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS
1
2
VDD = 18V, VIN = VDD or GND
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
3
1
2
VDD = 18V
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
3
1
2
VDD = 18V
Output Voltage
Output Voltage
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
N Threshold Voltage
P Threshold Voltage
Functional
VOL15
VOH15
IOL5
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
VNTH
VPTH
F
VDD = 15V, No Load
VDD = 15V, No Load (Note 3)
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
VDD = 10V, VOUT = 9.5V
VDD = 15V, VOUT = 13.5V
VDD = 10V, ISS = -10A
VSS = 0V, IDD = 10A
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
VIL
VIH
VIL
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
VDD = 5V, VOH > 4.5V, VOL < 0.5V
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
3
1, 2, 3
1, 2, 3
1
1
1
1
1
1
1
1
1
7
7
8A
8B
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
LIMITS
TEMPERATURE
+25
o
C
+125
o
C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
-
3.5
-
11
1.5
-
4
-
V
V
V
V
MIN
-
-
-
-100
-1000
-100
-
-
-
-
MAX
10
1000
10
-
-
-
100
1000
100
50
-
-
-
-
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
UNITS
A
A
A
nA
nA
nA
nA
nA
nA
mV
V
mA
mA
mA
mA
mA
mA
mA
V
V
V
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
(NOTE 1)
VDD = 20V, VIN = VDD or GND
+25
o
C, +125
o
C, -55
o
C 14.95
0.53
1.4
3.5
-
-
-
-
-2.8
0.7
VOH > VOL <
VDD/2 VDD/2
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
FN3295 Rev 0.00
December 1992
Page 2 of 8
CD4015BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS TEMPERATURE
9
10, 11
VDD = 5V, VIN = VDD or GND
9
10, 11
TTHL
TTLH
FCL
VDD = 5V, VIN = VDD or GND
9
10, 11
VDD = 5V, VIN = VDD or GND
9
10, 11
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
LIMITS
MIN
-
-
-
-
-
-
3
3/1.35
MAX
320
432
400
540
200
270
-
-
UNITS
ns
ns
ns
ns
ns
ns
MHz
MHz
PARAMETER
Propagation Delay
Clock To Q
Propagation Delay
Reset To Q
Transition Time
SYMBOL
TPHL1
TPLH1
TPHL2
CONDITIONS
(NOTE 1, 2)
VDD = 5V, VIN = VDD or GND
Maximum Clock Input
Frequency
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55
o
C and +125
o
C limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
VDD = 5V, VIN = VDD or GND
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Input Voltage Low
Input Voltage High
VOL
VOL
VOH
VOH
IOL5
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
VIL
VIH
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
VDD = 10V, VOUT = 9.5V
VDD =15V, VOUT = 13.5V
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V, VOH > 9V, VOL < 1V
NOTES
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
TEMPERATURE
-55
o
C, +25
o
C
+125 C
-55
o
C, +25
o
C
+125
o
C
-55 C, +25 C
+125
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+125
o
C
-55
o
C
+125
o
C
-55
o
C
C
C
+125
o
+125
o
-55
o
o
o
o
MIN
-
-
-
-
-
-
-
-
4.95
9.95
0.36
0.64
0.9
1.6
2.4
4.2
-
-
-
-
-
-
-
-
-
+7
MAX
5
150
10
300
10
600
50
50
-
-
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
-0.9
-1.6
-2.4
-4.2
3
-
UNITS
A
A
A
A
A
A
mV
mV
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
-55
o
C
C
+125
o
C
-55
o
C
+125
o
C
-55
o
C
+125
o
C
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
FN3295 Rev 0.00
December 1992
Page 3 of 8
CD4015BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
LIMITS
PARAMETER
Propagation Delay
Clock To Q
Propagation Delay
Reset To Q
Transition Time
Maximum Clock Input
Frequency
Minimum Data Setup
Time
SYMBOL
TPHL1
TPLH1
TPHL2
TTHL
TTLH
FCL
TS
CONDITIONS
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
Clock Rise and Fall Time
TRCL
TFCL
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Clock Pulse
Width
TWCL
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Reset Pulse
Width
TWR
VDD = 5V
VDD = 10V
VDD = 15V
Input Capacitance
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on
initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
N Threshold Voltage
N Threshold Voltage
Delta
P Threshold Voltage
P Threshold Voltage
Delta
Functional
SYMBOL
IDD
VNTH
VNTH
VPTH
VPTH
F
CONDITIONS
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10A
VDD = 10V, ISS= -10A
VSS = 0V, IDD = 10A
VSS = 0V, IDD = 10A
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
1, 2, 3, 4
+25
o
C
NOTES
1, 4
1, 4
1, 4
1, 4
1, 4
1
TEMPERATURE
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
MIN
-
-2.8
-
0.2
-
VOH >
VDD/2
-
MAX
25
-0.2
1
2.8
1
VOL <
VDD/2
1.35 x
+25
o
C
Limit
UNITS
A
V
V
V
V
V
CIN
Any Input
NOTES
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
2, 3
2, 3
2, 3
1, 2
TEMPERATURE
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
MIN
-
-
-
-
-
-
6
8.5
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX
160
120
200
160
100
80
-
-
70
40
30
15
15
15
180
80
50
200
80
60
7.5
UNITS
ns
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
s
s
s
ns
ns
ns
ns
ns
ns
pF
ns
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25
o
C limit.
4. Read and Record
FN3295 Rev 0.00
December 1992
Page 4 of 8
CD4015BMS
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25
O
C
PARAMETER
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
IOL5
IOH5A
1.0A
20% x Pre-Test Reading
20% x Pre-Test Reading
DELTA LIMIT
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
Group A
Group B
Subgroup B-5
Subgroup B-6
Group D
MIL-STD-883
METHOD
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
GROUP A SUBGROUPS
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9, Deltas
1, 7, 9
1, 7, 9, Deltas
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
1, 2, 3, 8A, 8B, 9
Subgroups 1, 2 3
Subgroups 1, 2, 3, 9, 10, 11
IDD, IOL5, IOH5A
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
5005
TEST
PRE-IRRAD
1, 7, 9
POST-IRRAD
Table 4
READ AND RECORD
PRE-IRRAD
1, 9
POST-IRRAD
Table 4
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
Static Burn-In 1
Note 1
Static Burn-In 2
Note 1
Dynamic Burn-
In Note 1
Irradiation
Note 2
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K
5%, VDD = 18V
0.5V
2. Each pin except VDD and GND will have a series resistor of 47K
5%;
Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V
0.5V
OPEN
2 - 5, 10 - 13
2 - 5, 10 - 13
-
2 - 5, 10 - 13
GROUND
1, 6 - 9, 14, 15
8
6, 8, 14
8
VDD
16
1, 6, 7, 9, 14 - 16
16
1, 6, 7, 9, 14 - 16
2 - 5, 10 - 13
1, 9
7, 15
9V
-0.5V
50kHz
25kHz
FN3295 Rev 0.00
December 1992
Page 5 of 8
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
