CY25023
Spread Spectrum Clock Generator for EMI
Reduction
Features
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Benefits
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SSCLK frequency: 52.0 MHz
Spread spectrum output with nominal 31.5 kHz modulation
frequency
❐
Center spread: ±1.0%
Input frequency
❐
External clock or crystal: 16.384 MHz
Integrated phase-locked loop (PLL)
Low cycle to cycle jitter
3.3V operation
Spread spectrum on and off function
Output enable function
Services most PC peripherals, networking, and consumer
applications.
Provides electromagnetic interference (EMI) reduction, to meet
regulatory agency electromagnetic compliance (EMC) require-
ments.
Eliminates the need for expensive and difficult to use overtone
crystals.
Internal PLL to generate up to 200 MHz output. Able to generate
custom frequencies from an external crystal or a driven source.
Suitable for most PC, consumer, and networking applications.
Application compatibility in standard and low power systems.
Provides ability to enable or disable spread spectrum with an
external pin.
Enables output clocks to High-Z state.
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Logic Block Diagram
XIN/CLKIN 1
OSC.
XOUT 8
CXOUT
CXIN
PLL
with
Modulation Control
Output
Programmable Configuration
Dividers
and
MUX
6 NC
5 SSCLK
OE
3
SSON 7
2
4
VDD VSS
Cypress Semiconductor Corporation
Document #: 38-07522 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 16, 2008
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CY25023
Pin Configurations
Figure 1. CY25023, 8-Pin SOIC
XIN/CLKIN
VDD
OE
VSS
1
2
3
4
8
7
6
5
XOUT
SSON
NC
SSCLK
Pin Description
Pin
1
2
3
4
5
6
7
8
Name
XIN/CLKIN
VDD
OE
VSS
SSCLK
NC
SSON
XOUT
3.3V Voltage Supply
Output Enable Pin: Active High. If OE = 1, SSCLK is enabled.
GND
Spread Spectrum Clock Output (52.0 MHz, ±1.0% center spread)
No Connect
Spread Spectrum Control. 1 = spread on, 0 = spread off.
Crystal Output. Leave this pin floating if external clock is used.
Description
Reference Crystal or Clock Input (16.384 MHz)
Table 1. Spread Spectrum Table
Part Number
CY25023SC–1
Spread Percentage
±1.0%
Document #: 38-07522 Rev. *A
Page 2 of 6
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CY25023
Absolute Maximum Condition
Supply Voltage (VDD)....................................... –0.5 to +7.0V
DC Input Voltage ....................................... –0.5V to V
DD
+0.5
Storage Temperature (Non-Condensing).... –55°C to +125°C
Junction Temperature ................................ –40°C to +125°C
Data Retention at Tj=125°C ...................................>10 years
Package Power Dissipation...................................... 350 mW
Static Discharge Voltage.......................................... > 2000V
(per MIL-STD-883, Method 3015)
Recommended Operating Conditions
Parameter
V
DD
T
A
C
LOAD
XIN/CLKIN
F
SSCLK
SS%
T
PU
Description
Supply Voltage
Ambient Temperature
Max. Load Capacitance at Pin 6
External Reference, Crystal or Clock Input
SSCLK Output Frequency, C
LOAD
= 15 pF
Spread Spectrum, CY25023SC–1
Power Up Time—for all VDDs to reach minimum specified voltage (power ramp
must be monotonic)
Min
3.13
0
Typ
3.30
Max
3.45
70
15
Unit
V
°C
pF
MHz
MHz
%
ms
16.384
52.0
±1.0
0.05
500
DC Electrical Specifications
Parameter
I
OH
I
OL
V
IH
V
IL
I
IH
I
IL
I
OZ
C
XIN
/C
XOUT[1]
C
IN[1]
I
VDD
Description
Output High Current
Output Low Current
Input High Voltage
Input Low Voltage
Input High Current,
OE and SSON pins
Input Low Current,
OE and SSON pins
Output Leakage Current
Capacitance at Pin 1 and Pin 8
Input Capacitance at Pin 3 and
Pin 7.
Supply Current
Condition
V
OH
= V
DD
– 0.5, V
DD
=3.3V (source)
V
OL
= 0.5, V
DD
= 3.3V (sink)
CMOS levels, 70% of V
DD
CMOS levels, 30% of V
DD
V
in
=V
DD
V
in
=V
SS
Three-state output, OE = 0
Input pins excluding XIN and XOUT
V
DD
= 3.45V, Fin = 16.384 MHz,
SSCLK = 52.0 MHz, C
LOAD
= 15 pF, OE =
SSON = V
DD
–10
22
5
30
Min
12
12
0.7V
DD
Typ
24
24
Max
Unit
mA
mA
V
V
μA
μA
μA
pF
pF
mA
0.3V
DD
10
10
10
7
40
AC Electrical Specifications
[1]
Parameter
DC
SR1
SR2
F
MOD
tj1
T
10
T
OE1
T
OE2
Description
Output Duty Cycle
Rising Edge Slew Rate
Falling Edge Slew Rate
Frequency Modulation
Peak Cycle to Cycle Jitter.
SSCLK pin.
PLL Lock Time
Output Disable time
(pin3 = OE)
Output Enable Time
(pin3 = OE)
Condition
SSCLK, measured at VDD/2
SSCLK from 20% to 80% of V
DD
SSCLK from 80% to 20% of V
DD
SSON = 1
SSCLK = 52.0 MHz. Spread on
Time from VDD minimum voltage to valid
output frequencies
Time from falling edge on OE to stopped
outputs, (Asynchronous)
Time from rising edge on OE to outputs at a
valid frequency, (Asynchronous)
Min
45
0.7
0.7
30.0
Typ
50
1.1
1.1
31.5
100
3
150
150
Max
55
1.5
1.5
33.0
200
5
300
300
Unit
%
V/ns
V/ns
kHz
ps
ms
ns
ns
Note
1. Guaranteed by Characterization, not 100% tested.
Document #: 38-07522 Rev. *A
Page 3 of 6
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CY25023
Figure 2. Application Circuit
[2,3]
Crystal
Power
XIN/CLKIN
1
8
XOUT
0.1uF
VDD
OE
VSS
3
4
CY25023
VDD
2
7
6
5
SSON
VDD
NC
SSCLK
Switching Waveforms
Figure 3. Duty Cycle Timing (DC = t
1A
/t
1B
)
OUTPUT
t
1A
t
1B
Figure 4. Output Rise/Fall Time (SSCLK and REFCLK)
V
DD
OUTPUT
0V
Tr
Tf
Output Rise time (Tr) = (0.6 x VDD) / SR1 (orSR3)
Output Fall time (Tf) = (0.6 x VDD) / SR2 (orSR4)
Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
Figure 5. Output Enable/Disable Timing
OUTPUT
ENABLE
V
DD
0V
V
IL
V
IH
T
OE2
CLKOUT
(Asynchronous)
T
OE1
High Impedance
Notes
2. IF an external clock is used, apply the clock to CLKIN(pin1) and leave XOUT(pin8) floating (unconnected).
3. If SSON(pin7) is LOW(V
SS
), the frequency modulation will be stopped on SSCLK pin(pin5)
Document #: 38-07522 Rev. *A
Page 4 of 6
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CY25023
Ordering Information
Part Number
CY25023SXC–1
[4]
CY25023SXC–1T
[4]
CY25023KSXC–1
CY25023KSXC–1T
Package Type
8-pin Small Outline Integrated Circuit (SOIC)
8-pin Small Outline Integrated Circuit (SOIC) – Tape and Reel
8-pin Small Outline Integrated Circuit (SOIC)
8-pin Small Outline Integrated Circuit (SOIC) – Tape and Reel
Product Flow
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Package Drawing and Dimensions
Figure 6.
8-lead (150-Mil) SOIC – S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
3. REFERENCE JEDEC MS-012
0.230[5.842]
0.244[6.197]
0.150[3.810]
0.157[3.987]
4. PACKAGE WEIGHT 0.07gms
PART #
S08.15 STANDARD PKG.
5
8
SZ08.15 LEAD FREE PKG.
0.189[4.800]
0.196[4.978]
SEATING PLANE
0.010[0.254]
0.016[0.406]
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
51-85066 *C
Note
4. Not recommended for new designs.
Document #: 38-07522 Rev. *A
Page 5 of 6
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