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FMS7950
Clock Multiplier
Features
•
•
•
•
•
•
•
•
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Crystal reference input
Up to 175 MHz of output frequency
Nine configurable outputs
Output enable pin
250 pS of output to output skew
300 pS of Cycle to Cycle Jitter
V
DD
Range of 3.3V ±0.2V
Commercial temperature range
Available in 32 pin LQFP
Feedback select (FBsel) pin allows for wider range of input
frequencies. When connected low, the lower input frequency
range is selected. This provides output frequencies of up to
eight times the input (see table 3). The higher input range is
allowed when FBsel is connected high.
There are four banks of outputs where each bank has a dedi-
cated divide select (DIV_SEL). Depending on the divide
selection, the outputs are one half, one quarter, or one eighth
of the VCO speed (see table 2 for details).
REF_SEL allows selection between crystal input or a clock
driven input. Connecting PLL_EN LOW and REF_SEL
HIGH will disable the Phase locked loop when the crystal
oscillator is not used. In this mode, FMS7950 will be in
clock buffer mode where any clock applied to TCLK will be
divided down to the four output banks per Table 2. This is
ideal for system diagnostic test.
FMS7950 operates at 3.3 Volts and is available in 32 pin LQFP.
Description
FMS7950 is a high speed clock synthesizer designed for clock
multiplication applications. It uses phase locked loop technol-
ogy to generate frequencies up to 175 MHz. It has four banks
of configurable outputs.
Block Diagram
REF_SEL
PLL_EN
OE
TCLK
QA
MUX
MUX
PLL
X1
X2
XTAL
OSC
QC0
QB
QC1
FBsel
QD0
QD1
DIV_SEL A
QD2
DIV_SEL B
DIV_SEL C
DIV_SEL D
QD4
Control
Logic
QD3
REV. 1.0.0 1/9/01
PRODUCT SPECIFICATION
FMS7950
Pin Assignments
REF_SEL
GNDOUT
QA
VDDOUT
GNDOUT
PLL_EN
TCLK
QB
VDDCOR
FBsel
DIV_SEL A
DIV_SEL B
DIV_SEL C
DIV_SEL D
GNDCOR
X1
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
32-PIN
LQFP
21
20
19
18
17
9 10 11 12 13 14 15 16
QD4
VDDOUT
GNDOUT
QD3
VDDOUT
QD2
X2
OE
QC0
VDDOUT
QC1
GNDOUT
QD0
VDDOUT
QD1
GNDOUT
Pin Description
Pin Name
VDDCOR
FBsel
DIV_SEL(A:D)
GNDCOR
X1
Pin #
1
2
3, 4, 5, 6
7
8
Pin Type
PWR
IN
IN
PWR
IN
Description
Power Connection.
Power supply for core logic and PLL
circuitry. Connect to 3.3 Volts nominal.
Feedback Select.
When high, the feedback divide is 8, and when
low, it is 16. It allows for a wider range of input frequencies.
Divider Select:
It divides the clock to a desirable value. See
table 2.
Ground Connection.
Ground for core logic and PLL circuitry.
Connect to the common system ground plane.
Crystal Connection.
An input connection for an external crystal
or oscillator. 18 pF internal cap. It can be used as an external
crystal connection or as an external reference frequency input.
Crystal Connection or External Reference Frequency.
This
pin has dual functions.
Output Enable.
When high, all outputs are in high impedance.
Normal operation when asserted low.
Power Connection.
Power supply for all the output buffers.
Connect to 3.3 Volts nominal.
Clock Outputs.
These outputs are multiple of the input.
Ground Connection.
Ground for all the outputs. Connect to
common system ground plane.
Test Clock.
When REF_SEL is high, all outputs are buffer copy
of TCLK. When REF_SEL is low, TCLK is disabled.
PLL Enable.
When low, PLL is bypassed.
Reference Select.
When low, crystal is used for input. When
high, TCLK is used for input.
X2
OE
VDDOUT
9
10
11, 15, 19, 23, 27
OUT
IN
PWR
OUT
PWR
IN
IN
IN
Q
A
; Q
B
; Q
C
(0:1); 12, 14, 16, 18, 20,
Q
D
(0:4)
22, 24, 26, 28
GNDOUT
TCLK
PLL_EN
REF_SEL
13, 17, 21, 25, 29
30
31
32
2
REV. 1.0.0 1/9/01
FMS7950
PRODUCT SPECIFICATION
Table 1. Functionality
REF_SEL
0
0
0
1
1
1
PLL_EN
0
0
1
0
0
1
OE
1
0
0
1
0
0
PLL
By Pass
By Pass
Enabled
By Pass
By Pass
Enabled
All Outputs
Hi-Z
Running
Running
Hi-Z
Running
Running
Input
XTAL
XTAL
XTAL
TCLK
TCLK
TCLK
Table 2. Input Versus Output Frequency
FBsel = 1
DIV_SEL A DIV_SEL B DIV_SEL C DIV_SEL D
QA
QB
QC
QD
QA
FBsel = 0
QB
QC
QD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4XRef 2XRef 2XRef 2XRef 8XRef 4XRef 4XRef 4XRef
4XRef 2XRef 2XRef
4XRef 2XRef
4XRef 2XRef
4XRef
4XRef
4XRef
4XRef
Ref
Ref
Ref
Ref
Ref
Ref
2XRef
Ref
Ref
Ref
Ref
Ref
Ref
Ref
Ref
Ref
Ref
8XRef 4XRef 4XRef 2XRef
8XRef 4XRef 2XRef 2XRef
8XRef 2XRef 4XRef 2XRef
8XRef 2XRef 2XRef 2XRef
4XRef 4XRef 4XRef 2XRef
4XRef 4XRef 2XRef 2XRef
4XRef 2XRef 4XRef 2XRef
4XRef 2XRef 2XRef 2XRef
2XRef 8XRef 4XRef 2XRef 4XRef
2XRef 2XRef 8XRef 2XRef 4XRef 4XRef
2XRef 8XRef 2XRef 2XRef 4XRef
2XRef 2XRef 2XRef 2XRef 4XRef 4XRef 4XRef 4XRef
2XRef 2XRef 2XRef
2XRef 2XRef
2XRef 2XRef
2XRef
2XRef
2XRef
2XRef
Ref
Ref
Ref
Ref
Ref
Ref
2XRef
Ref
Ref
2XRef 4XRef 4XRef 2XRef 4XRef
2XRef 2XRef 4XRef 2XRef 4XRef 4XRef
2XRef 4XRef 2XRef 2XRef 4XRef
Note:
1. Reference input could be either crystal input or TCLK input.
Table 3. Divide Select Functionality
DIV_SEL A
0
1
DIV_SEL B
0
1
DIV_SEL D
0
1
DIV_SEL D
0
1
QA
÷
2
÷
4
QB
÷
4
÷
8
QC
÷
4
÷
8
QD
÷
4
÷
8
REV. 1.0.0 1/9/01
3
PRODUCT SPECIFICATION
FMS7950
Absolute Maximum Ratings
Symbol
V
DD
, V
IN
T
STG
T
B
T
A
Parameter
Voltage on any pin with respect to ground
Storage Temperature
Ambient Temperature
Operating Temperature
Ratings
-0.5 to 7.0
-65 to 150
-55 to 125
0 to 70
Units
V
°C
°C
°C
Stresses greater than those listed in the table may cause permanent damage to the device. These represent a stress rating only.
Operation of the device at these or any other conditions above those specified in the operating sections of this specification is
not implied. Maximum conditions for extended periods may effect reliability.
DC Electrical Characteristics
T
A
= 0 to 70°C; Supply Voltage 3.3 V ±0.2V (unless otherwise stated)
Parameter
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Input Capacitance
(1)
Supply Current
Clock Stabilization
(1)
Symbol
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
C
IN
I
DD
T
STAB
Outputs loaded
From V
DD
= 3.3V to 1% Target
V
IN
= 0
V
IN
= V
DD
I
OL
= 40 mA
I
OH
= –40mA
2.2
7.0
200
10
2.0
-10
-30
10
30
0.5
Conditions
Min.
Typ.
Max.
0.8
Units
V
V
µA
µA
V
V
pF
mA
mS
Note:
1. Guaranteed by design, not subject to 100% production testing.
AC Electrical Characteristics
T
A
= 0 to 70°C; Supply Voltage V
DD
= 3.3V ±0.2V, C
L
= 10 pF (unless otherwise stated)
Parameter
Input Frequency Range
Output Frequency Range
Symbol
F
INPUT
F
OUT
Conditions
FBsel = 1
FBsel = 0
Q
A
; DIV_SEL A = 0V
Q
B
, Q
C
& Q
D
;
DIV_SEL B, C, D = 0V
Output to Output Skew
Rise Time
(1)
Fall Time
(1)
Duty Cycle
(1)
Jitter (Cycle-Cycle)
T
SK1
T
R
T
F
D
T
T
JIT
V
TH
= V
DD
/2; DIV_SEL A = 0
V
TH
= V
DD
/2; DIV_SEL A = 1
0.8 to 2.0V
2.0 to 0.8V
V
TH
= V
DD
/2
QA: DIV_SEL A = 0
QA: DIV_SEL A = 1
QB Output
QC(0:1) Outputs
QD(0:4) Outputs
Note:
1. Guaranteed by design, not subject to 100% production testing.
Min.
25
12
Typ.
Max.
43
22
175
88
Units
MHz
MHz
MHz
MHz
pS
nS
nS
%
pS
400
-300
0.10
0.10
45
100
750
300
1.0
1.0
55
450
200
200
300
375
4
REV. 1.0.0 1/9/01
FMS7950
PRODUCT SPECIFICATION
Parameter Measurement Information
Duty Cycle (D
T
)
T
1
T
2
D
T
=
1.5V
1.5V
1.5V
T
2
x 100
T
1
Rise/Fall Time (T
R
/T
F
)
2.0V
Output
0.8V
2.0V
0.8V
0V
3.3V
T
R
T
F
Output to Output Skew (T
SK1
)
1.5V
Q
0
1.5V
Any Output
T
SK1
REV. 1.0.0 1/9/01
5
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