Intel
®
Atom™ Processor E6x5C
Series
Product Preview Datasheet
December 2010
Revision 001US
Order Number: 324602-001US
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®
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®
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®
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Intel
®
Atom™ Processor E6x5C Series
Product Preview Datasheet
2
December 2010
Order Number: 324602-001US
Contents—Intel
®
Atom™ Processor E6x5C Series
Contents
1.0
Introduction
............................................................................................................ 23
1.1
Document Organization...................................................................................... 24
1.2
Intel
®
Atom™ Processor E6xx Series Introduction ................................................. 24
1.3
Terminology ..................................................................................................... 24
1.4
Reference Documents ........................................................................................ 26
1.5
Components Overview ....................................................................................... 27
1.5.1 Low-Power Intel
®
Architecture Core.......................................................... 27
1.5.2 System Memory Controller ...................................................................... 28
1.5.3 Graphics ............................................................................................... 28
1.5.4 Video Decode ........................................................................................ 28
1.5.5 Video Encode......................................................................................... 29
1.5.6 Display Interfaces .................................................................................. 29
1.5.6.1 LVDS Display Interface .............................................................. 29
1.5.6.2 Serial DVO (SDVO) Display Interface ........................................... 29
1.5.7 PCI Express* ......................................................................................... 29
1.5.8 LPC Interface......................................................................................... 29
1.5.9 Intel
®
High Definition Audio
b
(Intel
®
HD Audio
b
) Controller ......................... 29
1.5.10 SMBus Host Controller ............................................................................ 30
1.5.11 General Purpose I/O (GPIO)..................................................................... 30
1.5.12 Serial Peripheral Interface (SPI) ............................................................... 30
1.5.13 Power Management ................................................................................ 30
1.5.14 Watchdog Timer (WDT)........................................................................... 30
1.5.15 Real Time Clock (RTC) ............................................................................ 31
1.6
FPGA Introduction ............................................................................................. 31
1.6.1 Core Architecture ................................................................................... 31
1.6.2 Transceivers .......................................................................................... 32
1.6.2.1 Key Transceiver Features ........................................................... 32
1.6.2.2 Block Diagram.......................................................................... 33
1.6.3 DSP Blocks ............................................................................................ 34
1.6.4 I/O Features .......................................................................................... 34
1.6.5 External Memory Interfaces ..................................................................... 34
1.6.6 Clock Management ................................................................................. 34
1.6.7 Remote System Upgrade ......................................................................... 35
1.6.8 Design Security...................................................................................... 35
1.6.9 JTAG Boundary Scan Testing.................................................................... 35
1.6.10 Software and Tools................................................................................. 35
1.7
Intel
®
Atom™ Processor E6x5C Series MCP Connection Details................................ 37
1.8
Intel
®
Atom™ Processor E6x5C Series SKU........................................................... 39
1.9
Intel
®
Atom™ Processor E6x5C Series Package ..................................................... 40
Signal Description
................................................................................................... 41
2.1
System Memory Signals ..................................................................................... 42
2.2
Integrated Display Interfaces .............................................................................. 43
2.2.1 LVDS Signals ......................................................................................... 43
2.2.2 Serial Digital Video Output (SDVO) Signals ................................................ 44
2.3
PCI Express* Signals ......................................................................................... 45
2.4
Intel
®
High Definition Audio
b
Interface Signals ...................................................... 45
2.5
LPC Interface Signals ......................................................................................... 46
2.6
SMBus Interface Signals..................................................................................... 46
2.7
SPI Interface Signals ......................................................................................... 46
2.8
Power Management Interface Signals ................................................................... 47
2.9
Real Time Clock Interface Signals ........................................................................ 48
2.0
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Order Number: 324602-001US
Intel
®
Atom™ Processor E6x5C Series
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3
Intel
®
Atom™ Processor E6x5C Series—Contents
2.10
2.11
2.12
2.13
2.14
2.15
3.0
JTAG and Debug Interface ..................................................................................49
Miscellaneous Signals and Clocks .........................................................................50
General Purpose I/O...........................................................................................53
Functional Straps...............................................................................................53
Processor Power and Ground Signals ....................................................................54
FPGA Pin List.....................................................................................................55
Pin States
................................................................................................................59
3.1
Pin Reset States ................................................................................................59
3.2
System Memory Signals .....................................................................................59
3.3
Integrated Display Interfaces ..............................................................................60
3.3.1 LVDS Signals .........................................................................................60
3.3.2 Serial Digital Video Output (SDVO) Signals.................................................60
3.4
PCI Express* Signals..........................................................................................61
3.5
Intel
®
High Definition Audio
b
Interface Signals ......................................................61
3.6
LPC Interface Signals .........................................................................................62
3.7
SMBus Interface Signals .....................................................................................62
3.8
SPI Interface Signals..........................................................................................62
3.9
Power Management Interface Signals ...................................................................62
3.10 Real Time Clock Interface Signals ........................................................................63
3.11 JTAG and Debug Interface ..................................................................................63
3.12 Miscellaneous Signals and Clocks .........................................................................63
3.13 General Purpose I/O...........................................................................................64
3.14 Integrated Termination Resistors .........................................................................64
Clock Domains
.........................................................................................................65
4.1
Processor Clock Domains ....................................................................................65
4.2
FPGA Clock Domains ..........................................................................................66
Register and Memory Mapping
.................................................................................67
5.1
Address Map .....................................................................................................67
5.2
Introduction ......................................................................................................68
5.3
System Memory Map..........................................................................................68
5.3.1 I/O Map.................................................................................................70
5.3.1.1 Fixed I/O Address Range ............................................................70
5.3.1.2 Variable I/O Address Range ........................................................71
5.3.2 PCI Devices and Functions .......................................................................71
5.4
Register Access Method ......................................................................................72
5.4.1 Direct Register Access .............................................................................72
5.4.1.1 Hard Coded IO Access................................................................72
5.4.1.2 IO BAR ....................................................................................72
5.4.1.3 Hard-Coded Memory Access........................................................72
5.4.1.4 Memory BAR.............................................................................72
5.4.2 Indirect Register Access...........................................................................73
5.4.2.1 PCI Config Space.......................................................................73
5.5
Bridging and Configuration..................................................................................73
5.5.1 Root Complex Topology Capability Structure...............................................73
5.5.1.1 Offset 0000h: RCTCL – Root Complex Topology Capabilities List ......74
5.5.1.2 Offset 0004h: ESD – Element Self Description ...............................74
5.5.1.3 Offset 0010h: HDD – Intel
®
High Definition Audio
b
Description........75
5.5.1.4 Offset 0018h: HDBA – Intel
®
High Definition Audio
b
Base Address ...76
5.5.2 Interrupt Pin Configuration.......................................................................76
5.5.2.1 Offset 3100h: D31IP – Device 31 Interrupt Pin ..............................77
5.5.2.2 Offset 3110h: D27IP – Device 27 Interrupt Pin ..............................77
5.5.2.3 Offset 3118h: D02IP – Device 2 Interrupt Pin................................78
5.5.2.4 Offset 3120h: D26IP – Device 26 Interrupt Pin ..............................78
5.5.2.5 Offset 3124h: D25IP – Device 25 Interrupt Pin ..............................79
4.0
5.0
Intel
®
Atom™ Processor E6x5C Series
Product Preview Datasheet
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December 2010
Order Number: 324602-001US
Contents—Intel
®
Atom™ Processor E6x5C Series
5.5.3
5.5.4
5.5.2.6 Offset 3128h: D24IP – Device 24 Interrupt Pin ............................. 79
5.5.2.7 Offset 312Ch: D23IP – Device 23 Interrupt Pin ............................. 80
5.5.2.8 Offset 3130h: D03IP – Device 3 Interrupt Pin ............................... 80
Interrupt Route Configuration .................................................................. 80
5.5.3.1 Offset 3140h: D31IR – Device 31 Interrupt Route ......................... 81
5.5.3.2 Offset 3148h: D27IR – Device 27 Interrupt Route ......................... 81
5.5.3.3 Offset 314Ah: D26IR – Device 26 Interrupt Route ......................... 82
5.5.3.4 Offset 314Ch: D25IR – Device 25 Interrupt Route ......................... 83
5.5.3.5 Offset 314Eh: D24IR – Device 24 Interrupt Route ......................... 83
5.5.3.6 Offset 3150h: D23IR – Device 23 Interrupt Route ......................... 84
5.5.3.7 Offset 3160h: D02IR – Device 2 Interrupt Route ........................... 84
5.5.3.8 Offset 3162h: D03IR – Device 3 Interrupt Route ........................... 85
General Configuration ............................................................................. 85
5.5.4.1 Offset 3400h: RC – RTC Configuration ......................................... 85
5.5.4.2 Offset 3410h: BNT– Boot Configuration........................................ 86
6.0
Memory Controller...................................................................................................
87
6.1
Overview ......................................................................................................... 87
6.1.1 DRAM Frequencies and Data Rates ........................................................... 87
6.2
DRAM Burst Length ........................................................................................... 87
6.3
DRAM Partial Writes........................................................................................... 87
6.4
DRAM Power Management .................................................................................. 87
6.4.1 Powerdown Modes .................................................................................. 88
6.4.2 Self Refresh Mode .................................................................................. 88
6.4.3 Dynamic Self Refresh Mode ..................................................................... 88
6.4.4 Page Management .................................................................................. 88
6.5
Refresh Mode.................................................................................................... 88
6.6
Supported DRAM Configurations .......................................................................... 89
6.7
Supported DRAM Devices ................................................................................... 90
6.8
Supported Rank Configurations ........................................................................... 90
6.9
Address Mapping and Decoding ........................................................................... 91
Graphics, Video, and Display
................................................................................... 93
7.1
Chapter Contents .............................................................................................. 93
7.2
Overview ......................................................................................................... 93
7.2.1 3D Graphics .......................................................................................... 93
7.2.2 Shading Engine Key Features ................................................................... 94
7.2.3 Vertex Processing................................................................................... 95
7.2.3.1 Vertex Transform Stages ........................................................... 95
7.2.3.2 Lighting Stages ........................................................................ 95
7.2.4 Pixel Processing ..................................................................................... 96
7.2.4.1 Hidden Surface Removal ............................................................ 96
7.2.4.2 Applying Textures and Shading................................................... 96
7.2.4.3 Final Pixel Formatting ................................................................ 96
7.2.5 Unified Shader ....................................................................................... 96
7.2.6 Multi Level Cache ................................................................................... 97
7.3
Video Encode.................................................................................................... 97
7.3.1 Supported Input Formats ........................................................................ 97
7.3.1.1 Encoding Pipeline...................................................................... 97
7.3.1.2 Encode Codec Support............................................................... 98
7.3.1.3 Encode Specifications Supported................................................. 98
7.4
Video Decode ................................................................................................... 99
7.4.1 Entropy Coding ...................................................................................... 99
7.4.1.1 Motion Compensation .............................................................. 100
7.4.1.2 Deblocking............................................................................. 100
7.4.1.3 Output Reference Frame Storage Format ................................... 100
7.4.1.4 Pixel Format........................................................................... 101
7.0
December 2010
Order Number: 324602-001US
Intel
®
Atom™ Processor E6x5C Series
Product Preview Datasheet
5
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