64-bit Intel
®
Xeon™ Processor
with 2 MB L2 Cache
Datasheet
September 2005
Document Number: 306249-002
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®
Xeon™ Processor with 2 MB L2 Cache may contain design defects or errors known as errata which may cause the product to
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2
Datasheet
Contents
1
Introduction....................................................................................................................... 11
1.1
1.2
1.3
2
2.1
2.2
Terminology......................................................................................................... 12
References .......................................................................................................... 14
State of Data ....................................................................................................... 15
Power and Ground Pins ...................................................................................... 17
Decoupling Guidelines ........................................................................................ 17
2.2.1 VCC Decoupling ..................................................................................... 17
2.2.2 VTT Decoupling...................................................................................... 17
2.2.3 Front Side Bus AGTL+ Decoupling ........................................................ 18
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking................................ 18
2.3.1 Front Side Bus Frequency Select Signals (BSEL[1:0]) .......................... 18
2.3.2 Phase Lock Loop (PLL) and Filter.......................................................... 19
Voltage Identification (VID).................................................................................. 20
Reserved Or Unused Pins................................................................................... 22
Front Side Bus Signal Groups............................................................................. 22
GTL+ Asynchronous and AGTL+ Asynchronous Signals ................................... 24
Test Access Port (TAP) Connection.................................................................... 24
Mixing Processors ............................................................................................... 25
Absolute Maximum and Minimum Ratings .......................................................... 25
Processor DC Specifications............................................................................... 26
2.11.1 Flexible Motherboard Guidelines (FMB)................................................. 26
2.11.2 VCC Overshoot Specification.................................................................31
2.11.3 Die Voltage Validation ............................................................................ 32
Package Mechanical Drawings ........................................................................... 36
Processor Component Keepout Zones ............................................................... 39
Package Loading Specifications ......................................................................... 39
Package Handling Guidelines ............................................................................. 40
Package Insertion Specifications ........................................................................ 40
Processor Mass Specifications ........................................................................... 40
Processor Materials............................................................................................. 40
Processor Markings............................................................................................. 41
Processor Pin-Out Coordinates........................................................................... 42
Signal Definitions................................................................................................. 45
64-bit Intel
®
Xeon™ Processor with 2 MB L2 Cache Pin Assignments .............. 55
5.1.1 Pin Listing by Pin Name ......................................................................... 55
5.1.2 Pin Listing by Pin Number ...................................................................... 63
Package Thermal Specifications ......................................................................... 71
6.1.1 Thermal Specifications ........................................................................... 71
Electrical Specifications................................................................................................... 17
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
3
Mechanical Specifications ................................................................................................ 35
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4
5
Signal Definitions.............................................................................................................. 45
4.1
5.1
Pin Listing......................................................................................................................... 55
6
Thermal Specifications .................................................................................................... 71
6.1
Datasheet
3
6.2
6.1.2 Thermal Metrology ................................................................................. 78
Processor Thermal Features............................................................................... 79
6.2.1 Thermal Monitor ..................................................................................... 79
6.2.2 Thermal Monitor 2 .................................................................................. 79
6.2.3 On-Demand Mode.................................................................................. 81
6.2.4 PROCHOT# Signal Pin .......................................................................... 81
6.2.5 FORCEPR# Signal Pin .......................................................................... 81
6.2.6 THERMTRIP# Signal Pin ....................................................................... 82
6.2.7 TCONTROL and Fan Speed Reduction................................................. 82
6.2.8 Thermal Diode........................................................................................ 82
Power-On Configuration Options ........................................................................ 85
Clock Control and Low Power States.................................................................. 85
7.2.1 Normal State .......................................................................................... 86
7.2.2 HALT or Enhanced HALT Power Down States ...................................... 86
7.2.3 Stop Grant State .................................................................................... 87
7.2.4 Enhanced HALT Snoop or HALT Snoop State, Stop Grant
Snoop State ........................................................................................... 88
7.2.5 Sleep State............................................................................................. 88
Demand Based Switching (DBS) with Enhanced Intel
SpeedStep
®
Technology..................................................................................... 89
Introduction ......................................................................................................... 91
Mechanical Specifications ................................................................................... 93
8.2.1 Boxed Processor Heatsink Dimensions (CEK) ...................................... 93
8.2.2 Boxed Processor Heatsink Weight....................................................... 101
8.2.3 Boxed Processor Retention Mechanism and
Heatsink Support (CEK) ....................................................................... 101
Electrical Requirements .................................................................................... 101
8.3.1 Fan Power Supply (Active CEK) .......................................................... 101
8.3.2 Boxed Processor Cooling Requirements ............................................. 103
Boxed Processor Contents ............................................................................... 104
Debug Port System Requirements.................................................................... 105
Target System Implementation ......................................................................... 105
9.2.1 System Implementation........................................................................ 105
Logic Analyzer Interface (LAI) .......................................................................... 105
9.3.1 Mechanical Considerations .................................................................. 106
9.3.2 Electrical Considerations...................................................................... 106
7
Features ........................................................................................................................... 85
7.1
7.2
7.3
8
Boxed Processor Specifications....................................................................................... 91
8.1
8.2
8.3
8.4
9
9.1
9.2
9.3
Debug Tools Specifications............................................................................................ 105
Figures
2-1
2-2
2-3
2-4
2-5
3-1
4
Phase Lock Loop (PLL) Filter Requirements ...................................................... 19
64-bit Intel
®
Xeon™ Processor and 64-bit Intel
®
Xeon™
MV 3.20 GHz Processor Load Current Vs. Time ................................................ 29
64-bit Intel
®
Xeon™ LV 3 GHz Processor Load Current Vs. Time ..................... 29
VCC Static and Transient Tolerance................................................................... 31
VCC Overshoot Example Waveform................................................................... 32
Processor Package Assembly Sketch ................................................................ 35
Datasheet
3-2
3-3
3-4
3-5
3-6
3-7
6-1
6-2
6-3
6-4
6-5
7-1
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
Processor Package Drawing (Sheet 1 of 2) ........................................................ 37
Processor Package Drawing (Sheet 2 of 2) ........................................................ 38
Processor Top-Side Markings (Example)............................................................ 41
Processor Bottom-Side Markings (Example) ...................................................... 41
Processor Pin-out Coordinates, Top View .......................................................... 42
Processor Pin-out Coordinates, Bottom View ..................................................... 43
64-bit Intel
®
Xeon™ Processor with 2 MB L2 Cache Thermal Profiles
A and B (PRB = 1)............................................................................................... 73
64-bit Intel
®
Xeon™ MV 3.20 GHz Processor Thermal Profiles
A and B (PRB = 1)............................................................................................... 75
64-bit Intel
®
Xeon™ LV Processor Thermal Profiles A and B (PRB = 0) ............ 77
Case Temperature (TCASE) Measurement Location ......................................... 78
Demand Based Switching Frequency and Voltage Ordering .............................. 80
Stop Clock State Machine ................................................................................... 87
1U Passive CEK Heatsink................................................................................... 91
2U Passive CEK Heatsink................................................................................... 92
Active CEK Heatsink (Representation Only) ....................................................... 92
Passive 64-bit Intel
®
Xeon™ Processor with 2 MB L2 Cache Thermal
Solution (2U and Larger) ..................................................................................... 93
Top-Side Board Keepout Zones (Part 1)............................................................. 94
Top-Side Board Keepout Zones (Part 2)............................................................. 95
Bottom-Side Board Keepout Zones..................................................................... 96
Board Mounting Hole Keepout Zones .................................................................97
Volumetric Height Keep-Ins................................................................................. 98
4-Pin Fan Cable Connector (For Active CEK Heatsink)...................................... 99
4-Pin Base Board Fan Header (For Active CEK Heatsink) ...............................100
Fan Cable Connector Pin Out for 4-Pin Active CEK Thermal Solution .............102
Tables
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
3-1
3-2
3-3
4-1
5-1
Datasheet
Features of the 64-bit Intel
®
Xeon™ Processor with 2 MB L2 Cache ................. 12
Core Frequency to Front Side Bus Multiplier Configuration ................................ 18
BSEL[1:0] Frequency Table ................................................................................ 19
Voltage Identification Definition 2, 3 .................................................................... 21
Front Side Bus Signal Groups............................................................................. 23
Signal Description Table ..................................................................................... 24
Signal Reference Voltages.................................................................................. 24
Absolute Maximum and Minimum Ratings .......................................................... 25
Voltage and Current Specifications ..................................................................... 27
VCC Static and Transient Tolerance................................................................... 30
VCC Overshoot Specifications ............................................................................ 31
BSEL[1:0] and VID[5:0] Signal Group DC Specifications.................................... 32
AGTL+ Signal Group DC Specifications ............................................................. 33
PWRGOOD Input and TAP Signal Group DC Specifications.............................. 33
GTL+ Asynchronous and AGTL+ Asynchronous Signal Group DC
Specifications ...................................................................................................... 34
VIDPWRGD DC Specifications ........................................................................... 34
Processor Loading Specifications ....................................................................... 39
Package Handling Guidelines ............................................................................. 40
Processor Materials............................................................................................. 40
Signal Definitions................................................................................................. 45
Pin Listing by Pin Name ...................................................................................... 55
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