HY27UH08AG(5/D)M Series
16Gbit (2Gx8bit) NAND Flash
16Gb NAND FLASH
HY27UH08AG5M
HY27UH08AGDM
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.6 / Dec. 2006
1
HY27UH08AG(5/D)M Series
16Gbit (2Gx8bit) NAND Flash
Document Title
16Gbit (2Gx8bit) NAND Flash Memory
Revision History
Revision
No.
0.0
Initial Draft.
1) Add HY27UH08AG5M & HY27UH08AGDM Products.
- Texts & figures are added.
2) Change Ac Characteristics
tR
Before
After
20
25
tCLS
0.1
Before
After
12
15
tAR
10
15
tWP
12
15
tDS
12
15
tREA
18
20
tWC
25
30
tRHZ
30
50
tADL
70
100
tCHZ
30
50
tRP
12
15
tCEA
25
35
tRC
25
30
Oct. 08. 2005
Preliminary
History
Draft Date
Sep. 08. 2005
Remark
Initial
3) Add tCRRH (100ns, Min)
- tCRRH: cache Read RE# High
4) Change 3rd Read ID
- 3rd Read ID is changed to C1h
- 3rd Byte of Device Identifier Table is added.
5) Change NOP
- Number of Partial Program Cycle in the same page is changed to 4.
6) Delete Concurrent Operation.
1) Change AC Characteristics
0.2
tREA
Before
After
1)
2)
3)
4)
0.3
Before
After
Rev. 0.6 / Dec. 2006
tCEA
35
30
tCS
20
25
20
25
Nov. 16. 2005
Preliminary
Add ECC algorithm. (1bit/512bytes)
Change NOP
Correct Read ID naming
Change DC characterics
I
CC1
Typ
30
30
Max
60
45
I
CC2
Typ
30
30
Max
60
45
I
CC3
Typ
30
30
Max
60
45
Jun. 20. 2006
Preliminary
HY27UH08AG(5/D)M Series
16Gbit (2Gx8bit) NAND Flash
Revision History
Revision
No.
0.4
0.5
0.6
1) Delete Preliminary.
1) Correct copy back function.
1) Delete PRE function.
2) Delete Lock & Unlock function.
3) Delete Auto Read function.
- Continued
History
Draft Date
Jul. 10. 2006
Sep. 27. 2006
Dec. 26. 2006
Remark
Rev. 0.6 / Dec. 2006
HY27UH08AG(5/D)M Series
16Gbit (2Gx8bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
NAND INTERFACE
- x8 width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
CHIP ENABLE DON'T CARE
- Simple interface with microcontroller
SERIAL NUMBER OPTION
HARDWARE DATA PROTECTION
Memory Cell Array
= (2K+ 64) Bytes x 64 Pages x 16,384 Blocks
PAGE SIZE
- x8 device : (2K + 64 spare) Bytes
: HY27UH08AG(5/D)M
DATA INTEGRITY
- 100,000 Program/Erase cycles (with 1bit/512byte ECC)
- 10 years Data Retention
PACKAGE
- HY27UH08AG5M-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27UH08AG5M-T (Lead)
- HY27UH08AG5M-TP (Lead Free)
- HY27UH08AGDM-MP
: 52-TLGA (12 x 17 x 1.0 mm)
- HY27UH08AGDM-MP (Lead Free)
- Program/Erase locked during Power transitions
STATUS REGISTER
ELECTRONIC SIGNATURE
- 1st cycle: Manufacturer Code
- 2nd cycle: Device Code.
SUPPLY VOLTAGE
- 3.3V device: VCC = 2.7 to 3.6V
: HY27UH08AG(5/D)M
BLOCK SIZE
- x8 device: (128K + 4K spare) Bytes
PAGE READ / PROGRAM
- Random access: 25us (max.)
- Sequential access: 30ns (min.)
- Page program time: 200us (typ.)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
CACHE PROGRAM MODE
- Internal Cache Register to improve the program
throughput
FAST BLOCK ERASE
- Block erase time: 2ms (Typ.)
Rev. 0.6 / Dec. 2006
HY27UH08AG(5/D)M Series
16Gbit (2Gx8bit) NAND Flash
1. SUMMARY DESCRIPTION
The HYNIX HY27UH08AG(5/D)M series is a 2Gx8bit with spare 64Mx8 bit capacity. The device is offered in 3.3V Vcc
Power Supply.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old
data is erased.
The device contains 16,384 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected
Flash cells.
A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in
typical 2ms on a 128K-byte(X8 device) block.
Data in the page mode can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and
data input/output as well as command input. This interface allows a reduced pin count and easy migration towards dif-
ferent densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin.
The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where
required, and internal verification and margining of data.
The modifying can be locked using the WP input pin.
The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multi-
ple memories the R/B pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the HY27UH08AG(5/D)M extended reliability of 100K pro-
gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
The chip could be offered with the CE don’t care function. This function allows the direct download of the code from
the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation.
The copy back function allows the optimization of defective blocks management: when a page program operation fails
the data can be directly programmed in another page inside the same array section without the time consuming serial
data insertion phase.
The cache program feature allows the data insertion in the cache register while the data register is copied into the
flash array. This pipelined program operation improves the program throughput when long files are written inside the
memory.
A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when con-
secutive pages have to be streamed out.
This device includes also extra features like OTP/Unique ID area, Read ID2 extension.
The HYNIX HY27UH08AG(5/D)M series is available in 48 - TSOP1 12 x 20 mm, 52 - TLGA 12X17mm.
1.1 Product List
PART NUMBER
HY27UH08AG5M
HY27UH08AGDM
ORIZATION
x8
x8
VCC RANGE
2.7V - 3.6 Volt
2.7V - 3.6 Volt
PACKAGE
48TSOP1
52TLGA
2. BUS OPERATION
Rev. 0.6 / Dec. 2006
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