MITSUBISHI MICROCOMPUTERS
M35045-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
DESCRIPTION
The M35045-XXXSP/FP is a TV screen display control IC. It uses a
silicon gate CMOS process and is housed in a 20-pin shrink DIP
package (M35045-XXXSP) or a 20-pin shrink SOP package
(M35045-XXXFP).
For M35045-001SP/FP that is a standard ROM version of M35045-
XXXSP/FP respectively, the character pattern is also mentioned.
PIN CONFIGURATION (TOP VIEW)
CPOUT
←
1
VIR
2
FEATURES
AC
→
3
CS
→
4
SCK
→
5
SIN
→
6
TCK
→
7
V
DD1
8
P6
←
9
P7
←
10
V
DD2
19
←
VERT
18
←
HOR
20
17
→
P5/B
16
→
P4
15
→
P3/G
14
→
P2
13
→
P1/R
12
→
P0/BLNK0
11
V
SS
M35045 - XXXSP
•
Screen composition .................................... 24 columns
×
12 lines
•
Number of characters displayed ................................... 288 (Max.)
•
Character composition ...................................... 12
×
18 dot matrix
•
Characters available .............................................. 256 characters
•
Character sizes available ..................... 4 (horizontal)
×
4 (vertical)
•
Display locations available
•
•
•
Horizontal direction .............................................. 1000 locations
Vertical direction .................................................. 1023 locations
Blinking .................................................................. Character units
Cycle : division of vertical synchronization signal into 64 or 32
Duty : 25%, 50%, or 75%
Data input .................................. By the 16-bit serial input function
Coloring
Character color ..................................................... Character unit
Background coloring ............................................. Character unit
Matrix-outline (shadow) coloring .............. 8 colors (RGB output)
Specified by register
Border coloring ......................................... 8 colors (RGB output)
Specified by register
Raster coloring ......................................... 8 colors (RGB output)
Specified by register
Blanking
Blanking off
Character size blanking
Border size blanking
Matrix-outline blanking
All blanking (all raster area)
Output ports
4 shared output ports (toggled between RGB output)
4 dedicated output ports
Display RAM erase function
Display input frequency range ................... F
OSC
= 30MHz-80MHz
Outline 20P4B
CPOUT
←
1
VIR
2
20
AC
→
3
CS
→
4
SCK
→
5
SIN
→
6
TCK
→
7
V
DD1
8
←
9
P6
P7
←
10
V
DD2
19
←
VERT
18
←
HOR
17
→
P5/B
16
→
P4
15
→
P3/G
14
→
P2
13
→
P1/R
12
→
P0/BLNK0
11
V
SS
M35045 - XXXFP
•
Outline 20P2Q-A
•
•
•
APPLICATION
Monitor
MITSUBISHI MICROCOMPUTERS
M35045-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
PIN DESCRIPTION
Pin
Number
1
Symbol
CPOUT
Pin name
Phase difference
Input/
Output
Output
Connect loop filter to this pin.
1pin
2.4kΩ
∗
1
0.1µF
∗
2
CPOUT
Function
4700pF
∗
2
∗
1 Use at 1% precision
∗
2 Use at 10% precision
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VIR
__
Frequency control
Auto-clear input
Chip select input
Serial clock input
Serial data input
Test clock
Power pin
Port P6 output
Port P7 output
Earthing pin
Port P0 output
Port P1 output
Port P2 output
Port P3 output
Port P4 output
Port P5 output
Horizontal synchro-
nization signal input
Vertical synchroni-
zation signal input
Power pin
–
Input
Input
Input
Input
Input
–
Output
Output
–
Output
Output
Output
Output
Output
Output
Input
Input
–
Connect to GND.
When “L”, this pin resets the internal IC circuit. Hysteresis input. Includes built-in pull-up
resistor.
This is the chip select pin, and when serial data transmission is being carried out, it goes
to “L”. Hysteresis input. Includes built-in pull-up resistor.
__
AC
__
CS
SCK
SIN
TCK
V
DD1
P6
P7
V
SS
P0/BLNK0
P1/R
P2
P3/G
P4
P5/B
HOR
VERT
V
DD2
When CS pin is “L”, SIN serial data is taken in when SCK rises. Hysteresis input. Built-in
pull-up resistor is included.
This is the pin for serial input of data and addresses for the display control register and
the display data memory. Hysteresis input. Includes built-in pull-up resistor.
Input for test. Please connect to GND using circuit earthing pin.
Please connect to +5V with the power pin.
This is the output port. Port data is set by PTD6.
This is the output port. Port data is set by PTD7.
Please connect to GND using circuit earthing pin.
This pin can be toggled between port pin output and BLNK0 signal output.
This pin can be toggled between port pin output and R signal output.
This is the output port. Port data is set by PTD2.
This pin can be toggled between port pin output and G signal output.
This is the output port. Port data is set by PTD4.
This pin can be toggled between port pin output and B signal output.
This pin inputs the horizontal synchronization signal. Hysteresis input.
This pin inputs the vertical synchronization signal. Hysteresis input.
Please connect to +5V with the power pin.
2
BLOCK DIAGRAM
CPOUT
1
18
19
HOR
VERT
CS
Clock oscillation
circuit for display
Polarity switching circuit
4
SCK
5
Input control circuit
SIN
Synchronous signal
switching circuit
6
V
DD1
H counter
8
Data control
circuit
Timing generator
Address control
circuit
V
DD2
20
AC
3
Display control
register
Display location
detection circuit
12 P0/BLNK0
13 P1/R
Polarity
switching
circuti
15 P3/G
17 P5/B
V
SS
11
VIR
2
Display RAM
Blinking circuit
Reading address
control circuit
14 P2
16 P4
Port output
control circuit
Display control
circuit
9
P6
TCK
Shift register
7
Display character ROM
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
M35045-XXXSP/FP
10 P7
MITSUBISHI MICROCOMPUTERS
3
MITSUBISHI MICROCOMPUTERS
M35045-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
MEMORY CONSTITUTION
Address 000
16
to 11F
16
are assigned to the display RAM, address
120
16
to 128
16
are assigned to the display control registers. The in-
ternal circuit is reset and all display control registers (address 120
16
to 128
16
) are set to “0” and display RAM (address 000
16
to 11F
16
)
__
are set to “FF
16
” when the AC pin level is “L”.
Memory constitution is shown in Figure 1.
SCREEN CONSTITUTION
The screen lines and rows are determined from each address of the
display RAM. The screen constitution is shown in Figure 2.
DAF
000
16
………
11F
16
120
16
121
16
122
16
123
16
124
16
125
16
126
16
127
16
128
16
Row
1
Line
1
000
16
018
16
2
030
16
3
048
16
4
060
16
5
6
7
8
9
10
11
12
4
0
………
0
0
0
0
0
0
0
0
0
0
DAE
BB
DAD
BG
DAC
BR
DAB
BLINK
Blink-
ing
DAA
B
DA9
G
DA8
R
DA7
C7
DA6
C6
DA5
C5
DA4
C4
DA3
C3
DA2
C2
DA1
C1
DA0
C0
Background
coloring
BB
0
0
0
0
0
0
0
0
0
BG
BR
Character color
Character code
BLINK
B
G
DIV9
R
DIV8
C7
DIV7
C6
DIV6
C5
DIV5
C4
DIV4
C3
DIV3
C2
DIV2
C1
DIV1
C0
DIV0
DIVS2 DIVS1 DIVS0 DIV10
PTD7 PTD6 PTD5
PTD4 PTD3 PTD2 PTD1 PTD0 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
HP9
VP9
HP8
VP8
HP7
VP7
HP6
VP6
HP5
VP5
HP4
VP4
HP3
VP3
HP2
VP2
HP1
VP1
HP0
VP0
SPACE2 SPACE1 SPACE0 TEST9
TEST3 TEST2 TEST1 TEST0
TEST5 TEST4 DSP11 DSP10 DSP9 DSP8 DSP7 DSP6 DSP5 DSP4 DSP3 DSP2 DSP1 DSP0
VSZ1H1 VSZ1H0 VSZ1L1 VSZ1L0 V1SZ1 V1SZ0 LIN9
LIN8
LIN7
LIN6
LIN5
LIN4
LIN3
LIN2
VSZ2H1 VSZ2H0 VSZ2L1 VSZ2L0 V18SZ1 V18SZ0 LIN17 LIN16 LIN15 LIN14 LIN13 LIN12 LIN11 LIN10
HSZ21 HSZ20 HSZ11 HSZ10 BETA14 TEST8 TEST7 TEST6
BLINK2 BLINK1 BLINK0 DSPON STOP RAMERS SYAD BLK1
FB
FG
FR
RB
RG
__
RR
BCOL
BLK0 POLH POLV VMASK
B/F
Fig. 1 Memory constitution
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
001
16
002
16
003
16
004
16
005
16
006
16
007
16
008
16
009
16
00A
16
00B
16
00C
16
00D
16
00E
16
00F
16
010
16
011
16
012
16
013
16
014
16
015
16
016
16
017
16
019
16
01A
16
01B
16
01C
16
01D
16
01E
16
01F
16
020
16
021
16
022
16
023
16
024
16
025
16
026
16
027
16
028
16
029
16
02A
16
02B
16
02C
16
02D
16
02E
16
02F
16
031
16
032
16
033
16
034
16
035
16
036
16
037
16
038
16
039
16
03A
16
03B
16
03C
16
03D
16
03E
16
03F
16
040
16
041
16
042
16
043
16
044
16
045
16
046
16
047
16
049
16
04A
16
04B
16
04C
16
04D
16
04E
16
04F
16
050
16
051
16
052
16
053
16
054
16
055
16
056
16
057
16
058
16
059
16
05A
16
05B
16
05C
16
05D
16
05E
16
05F
16
061
16
062
16
063
16
064
16
065
16
066
16
067
16
068
16
069
16
06A
16
06B
16
06C
16
06D
16
06E
16
06F
16
070
16
071
16
072
16
073
16
074
16
075
16
076
16
077
16
078
16
079
16
07A
16
07B
16
07C
16
07D
16
07E
16
07F
16
080
16
081
16
082
16
083
16
084
16
085
16
086
16
087
16
088
16
089
16
08A
16
08B
16
08C
16
08D
16
08E
16
08F
16
090
16
091
16
092
16
093
16
094
16
095
16
096
16
097
16
098
16
099
16
09A
16
09B
16
09C
16
09D
16
09E
16
09F
16
0A0
16
0A1
16
0A2
16
0A3
16
0A4
16
0A5
16
0A6
16
0A7
16
0A8
16
0A9
16
0AA
16
0AB
16
0AC
16
0AD
16
0AE
16
0AF
16
0B0
16
0B1
16
0B2
16
0B3
16
0B4
16
0B5
16
0B6
16
0B7
16
0B8
16
0B9
16
0BA
16
0BB
16
0BC
16
0BD
16
0BE
16
0BF
16
0C0
16
0C1
16
0C2
16
0C3
16
0C4
16
0C5
16
0C6
16
0C7
16
0C8
16
0C9
16
0CA
16
0CB
16
0CC
16
0CD
16
0CE
16
0CF
16
0D0
16
0D1
16
0D2
16
0D3
16
0D4
16
0D5
16
0D6
16
0D7
16
0D8
16
0D9
16
0DA
16
0DB
16
0DC
16
0DD
16
0DE
16
0DF
16
0E0
16
0E1
16
0E2
16
0E3
16
0E4
16
0E5
16
0E6
16
0E7
16
0E8
16
0E9
16
0EA
16
0EB
16
0EC
16
0ED
16
0EE
16
0EF
16
0F0
16
0F1
16
0F2
16
0F3
16
0F4
16
0F5
16
0F6
16
0F7
16
0F8
16
0F9
16
0FA
16
0FB
16
0FC
16
0FD
16
0FE
16
0FF
16
100
16
101
16
102
16
103
16
104
16
105
16
106
16
107
16
108
16
109
16
10A
16
10B
16
10C
16
10D
16
10E
16
10F
16
110
16
111
16
112
16
113
16
114
16
115
16
116
16
117
16
118
16
119
16
11A
16
11B
16
11C
16
11D
16
11E
16
11F
16
*
The hexadecimal numbers in the boxes show the display RAM address.
Fig. 2 Screen constitution
MITSUBISHI MICROCOMPUTERS
M35045-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
REGISTERS DESCRIPTION
(1) Address 120
16
Contents
DA
Register
Status
0
0
DIV0
1
F
OSC
= f
H
×
N1
0
1
DIV1
1
0
2
DIV2
1
0
3
DIV3
1
0
4
DIV4
1
0
5
DIV5
1
0
6
DIV6
1
0
7
DIV7
1
0
8
DIV8
1
0
9
DIV9
1
0
A
DIV10
1
0
B
DIVS0
1
0
C
DIVS1
1
0
D
DIVS2
1
Can not be used.
__
Remarks
Function
Set multiply value (frequency value) of horizontal synchronous fre-
quency.
Display frequency is computed as
shown below.
10
N1 =
n=0
Σ
(DIVn
×
2
n
)
F
OSC
[MHz] : Display frequency
: Horizontal synchronous
f
H
[kHz]
signal frequency to HOR
pin.
N1
: Shown left
Set display frequency F
OSC
to within
30MHz to 80MHz range.
When display frequency F
OSC
, set fre-
quency value N2 in association with
DIVS0 and DIVS1.
N1: frequency value
Set frequency value N2
DIVS
1
0
0
1
1
0
0
1
0
1
Frequency
value N2
Division into 2
Division into 3
Division into 4
Do not set
Set frequency value N2 in association
with display frequency range.
Display frequency
55 ~ 80
40 ~ 55
30 ~ 40
Frequency value N2
Division into 2
Division into 3
Division into 4
It should be fixed to “0”.
Note: The mark
⁄
around the status value means the reset status by the “L” level is input to AC pin.
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
