MITSUBISHI MICROCOMPUTERS
New
p
uct
rod
M37733S4BFP
16-BIT CMOS MICROCOMPUTER
DESCRIPTION
The M37733S4BFP is a microcomputer using the 7700 Family core.
This microcomputer has a CPU and a bus interface unit. The CPU is
a 16-bit parallel processor that can be an 8-bit parallel processor,
and the bus interface unit enhances the memory access efficiency to
execute instructions fast. This microcomputer also includes a 32 kHz
oscillation circuit, in addition to the RAM, multiple-function timers,
serial I/O, A-D converter, and so on.
qProgrammable
input/output
(ports P4, P5, P6, P7, P8) ........................................................ 37
qClock
generating circuit ........................................ 2 circuits built-in
APPLICATION
Control devices for general commercial equipment such as office
automation, office equipment, personal information equipment, and
so on.
Control devices for general industrial equipment such as
communication equipment, and so on.
FEATURES
qNumber
of basic instructions .................................................. 103
qMemory
size
RAM ................................................ 2048 bytes
qInstruction
execution time
The fastest instruction at 25 MHz frequency ...................... 160 ns
qSingle
power supply .................................................... 5 V ± 10 %
qLow
power dissipation (At 25 MHz frequency)....... 47.5 mW (Typ.)
qInterrupts
............................................................ 19 types, 7 levels
qMultiple-function
16-bit timer ................................................. 5 + 3
qSerial
I/O (UART or clock synchronous)..................................... 3
q10-bit
A-D converter .............................................. 8-channel inputs
q12-bit
watchdog timer
PIN CONFIGURATION (TOP VIEW)
P8
4
/
CTS
1
/
RTS
1
P8
5
/CLK
1
P8
6
/R
X
D
1
P8
7
/T
X
D
1
P0
0
/A
0
P0
1
/A
1
P0
2
/A
2
P0
3
/A
3
P0
4
/A
4
P0
5
/A
5
P0
6
/A
6
P0
7
/A
7
P1
0
/A
8
/D
8
P1
1
/A
9
/D
9
P1
2
/A
10
/D
10
P1
3
/A
11
/D
11
P1
4
/A
12
/D
12
P1
5
/A
13
/D
13
P1
6
/A
14
/D
14
P1
7
/A
15
/D
15
P2
0
/A
16
/D
0
P2
1
/A
17
/D
1
P2
2
/A
18
/D
2
P2
3
/A
19
/D
3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P8
3
/T
X
D
0
P8
2
/R
X
D
0
/CLKS
0
P8
1
/CLK
0
P8
0
/
CTS
0
/
RTS
0
/CLKS
1
V
CC
AV
CC
V
REF
AV
SS
V
SS
P7
7
/AN
7
/X
CIN
P7
6
/AN
6
/X
COUT
P7
5
/AN
5
/
AD
TRG
/T
X
D
2
P7
4
/AN
4
/R
X
D
2
P7
3
/AN
3
/CLK
2
P7
2
/AN
2
/
CTS
2
P7
1
/AN
1
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
40
39
38
37
36
35
34
M37733S4BFP
33
32
31
30
29
28
27
26
25
P2
4
/A
20
/D
4
P2
5
/A
21
/D
5
P2
6
/A
22
/D
6
P2
7
/A
23
/D
7
P3
0
/
R
/
W
P3
1
/
BHE
P3
2
/ALE
P3
3
/
HLDA
V
SS
E
X
OUT
X
IN
RESET
CNV
SS
BYTE
HOLD
P7
0
/AN
0
P6
7
/TB2
IN
/
SUB
P6
6
/TB1
IN
P6
5
/TB0
IN
P6
4
/
INT
2
P6
3
/
INT
1
P6
2
/
INT
0
P6
1
/TA4
IN
P6
0
/TA4
OUT
P5
7
/TA3
IN
/
KI
3
/RTP1
3
P5
6
/TA3
OUT
/
KI
2
/RTP1
2
P5
5
/TA2
IN
/
KI
1
/RTP1
1
P5
4
/TA2
OUT
/
KI
0
/RTP1
0
P5
3
/TA1
IN
/RTP0
3
P5
2
/TA1
OUT
/RTP0
2
P5
1
/TA0
IN
/RTP0
1
P5
0
/TA0
OUT
/RTP0
0
P4
7
P4
6
P4
5
P4
4
P4
3
P4
2
/
1
Outline 80P6N-A
RDY
2
Reset input
RESET
M37733S4BFP BLOCK DIAGRAM
V
CC
AV
CC
(0V)
V
SS
CNVss
(0V)
AV
SS
Reference
External data bus width
voltage input
selection input
V
REF
BYTE
pro
New
Clock input Clock output
X
IN
X
OUT
Enable
output
E
d
X
CIN
X
COUT
Instruction Register(8)
uct
Clock Generating Circuit
Incrementer(24)
Stack Pointer S(16)
Index Register Y(16)
Index Register X(16)
Accumulator B(16)
Data Buffer DB
L
(8)
Data Bank Register DT(8)
Data Buffer DB
H
(8)
Input Butter Register IB(16)
Program Address Register PA(24)
Processor Status Register PS(11)
Program Counter PC(16)
Direct Page Register DPR(16)
Data Address Register DA(24)
Instruction Queue Buffer Q
0
(8)
Instruction Queue Buffer Q
2
(8)
Program Bank Register PG(8)
Instruction Queue Buffer Q
1
(8)
Incrementer/Decrementer(24)
Accumulator A(16)
Arithmetic Logic
Unit(16)
Timer TA4(16)
Watchdog Timer
Timer TB2(16)
UART2(9)
UART1(9)
UART0(9)
A-D Converter(10)
Timer TB1(16)
Timer TB0(16)
Timer TA3(16)
RAM
Timer TA2(16)
Data Bus(Odd)
2048 bytes
Timer TA1(16)
Data Bus(Even)
Address Bus
Timer TA0(16)
X
COUT
X
CIN
P8(8)
P7(8)
P6(8)
P5(8)
P4(5)
Address higher middler/data (16)
Address lower (8)
1
RDY HOLD HLDA ALE BHE
R/
W
MITSUBISHI MICROCOMPUTERS
M37733S4BFP
16-BIT CMOS MICROCOMPUTER
Input/Output
port P8
Input/Output
port P7
Input/Output
port P6
Input/Output
port P5
Input/Output
port P4
Address bus/Data bus
Address bus
MITSUBISHI MICROCOMPUTERS
New
p
t
duc
ro
M37733S4BFP
16-BIT CMOS MICROCOMPUTER
FUNCTIONS OF M37733S4BFP
Parameter
Number of basic instructions
Instruction execution time
Memory size
Input/Output ports
Multi-function timers
Serial I/O
A-D converter
Watchdog timer
Interrupts
Clock generating circuit
Supply voltage
Power dissipation
Input/Output characteristic
Memory expansion
Operating temperature range
Device structure
Package
Input/Output voltage
Output current
Functions
103
160 ns (the fastest instruction at external clock 25 MHz frequency)
2048 bytes
8-bit
!
4
5-bit
!
1
16-bit
!
5
16-bit
!
3
(UART or clock synchronous serial I/O)
!
3
10-bit
!
1 (8 channels)
12-bit
!
1
3 external types, 16 internal types
Each interrupt can be set to the priority level (0 – 7.)
2 circuits built-in (externally connected to a ceramic resonator or a
quartz-crystal oscillator)
5 V ± 10 %
47.5 mW (at external clock 25 MHz frequency)
5V
5 mA
Maximum 16 Mbytes
–20 to 85 °C
CMOS high-performance silicon gate process
80-pin plastic molded QFP (80P6N-A)
RAM
P5 – P8
P4
TA0, TA1, TA2, TA3, TA4
TB0, TB1, TB2
3
MITSUBISHI MICROCOMPUTERS
pro
New
Pin
Vcc,
Vss
CNVss
_____
RESET
d
uct
M37733S4BFP
16-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Name
Input/Output
Power source
Apply 5 V ± 10 % to Vcc and 0 V to Vss.
CNVss input
Reset input
Clock input
Clock output
Enable output
Bus width
selection input
Input
Input
Input
Output
Output
Input
Functions
X
IN
_
X
OUT
E
BYTE
AVcc,
AVss
V
REF
Analog power
source input
Reference
voltage input
P0
0
/A
0
–
Address (low-
P0
7
/A
7
order) output
P1
0
/A
8
/D
8
– Address (middle
P1
7
/A
15
/D
15
-order)
output/data
(high-order) I/O
P2
0
/A
16
/D
0
– Address (high-
P2
7
/A
23
/D
7
order)
output/data
(low-order) I/O
_
P3
0
/R/
W
Read/Write
output
___
P3
1
/
BHE
Byte high
enable output
P3
2
/ALE
Address latch
enable output
____
P3
3
/
HLDA Hold acknow-
HOLD
___
Connect to Vcc.
When “L” level is applied to this pin, the microcomputer enters the reset state.
These are pins of main-clock generating circuit. Connect a ceramic resonator or a quartz-crystal
oscillator between X
IN
and X
OUT
. When an external clock is used, the clock source should be
connected to the X
IN
pin, and the X
OUT
pin should be left open.
_
When output level of
E
signal is “L”, data/instruction read or data write is performed.
This pin determines whether the external data bus has an 8-bit width or a 16-bit width.
The data bus has a 16-bit width when “L” signal is input and an 8-bit width when “H” signal
is input.
Power source input pin for the A-D converter. Externally connect AVcc to Vcc and AVss to Vss.
This is reference voltage input pin for the A-D converter.
Address (A
0
– A
7
) is output.
When the BYTE pin is set to “L” and external data bus has a 16-bit width, high-order data
(D
8
– D
15
) is input/output or an address (A
8
– A
15
) is output. When the BYTE pin is “H” and an
external data bus has an 8-bit width, only address (A
8
– A
15
) is output.
Low-order data (D
0
– D
7
) is input/output or an address (A
16
– A
23
) is output.
Input
Output
I/O
I/O
Output
Output
Output
Output
Input
Input
Output
I/O
I/O
I/O
“H” indicates the read status and “L” indicates the write status.
“L” is output when an odd-numbered address is accessed.
This is used to retrieve only the address from address and data multiplex signal.
This outputs “L” level when the microcomputer enters hold state after a hold request is accepted.
____
____
RDY
ledge output
Hold request
input
Ready input
P4
2
/
1
P4
3
– P4
7
P5
0
– P5
7
P6
0
– P6
7
Clock output
I/O port P4
I/O port P5
I/O port P6
P7
0
– P7
7
I/O port P7
I/O
P8
0
– P8
7
I/O port P8
I/O
This is an input pin for
HOLD
request signal. The microcomputer enters into hold state while this
signal is “L”.
___
This is an input pin for
RDY
signal. The microcomputer enters into ready state while this signal is
“L”.
This pin outputs the clock
1
.
These pins become a 5-bit I/O port. An I/O direction register is available so that each pin can be
programmed for input or output. These ports are in the input mode when reset.
In addition to having the same functions as port P4,
__ __
also function as I/O pins for timers
these pins
A0 to A3 and input pins for key input interrupt input (
KI
0
–
KI
3
).
In addition to having the same functions as port
___
these pins also function as I/O pins for timer
P4,
___
A4, input pins for external interrupt input (
INT
0
–
INT
2
) and input pins for timers B0 to B2. P6
7
also
functions as sub-clock
SUB
output pin.
In addition to having the same functions as port P4, these pins function as input pins for A-D
converter. P7
2
to P7
5
also function as I/O pins for UART2. Additionally, P7
6
and P7
7
have the
function as the output pin (X
COUT
) and the input pin (X
CIN
) of the sub-clock (32 kHz) oscillation
circuit, respectively. When P7
6
and P7
7
are used as the X
COUT
and X
CIN
pins, connect a resonator
or an oscillator between the both.
In addition to having the same functions as port P4, these pins also function as I/O pins for UART
0 and UART 1.
4
MITSUBISHI MICROCOMPUTERS
New
p
t
duc
ro
M37733S4BFP
16-BIT CMOS MICROCOMPUTER
BASIC FUNCTION BLOCKS
The M37733S4BFP has the same functions as the
M37733MHBXXXFP except for the following :
(1) The memory map is different.
(2) The processor mode is different.
(3) The reset circuit is different.
(4) Pulse output port mode of timer A is available.
(5) The function of ROM area modification is not available.
MEMORY
The memory map is shown in Figure 1. The address space has a
capacity of 16 Mbytes and is allocated to addresses from 0
16
to
FFFFFF
16
. The address space is divided by 64-Kbyte unit called bank.
The banks are numbered from 0
16
to FF
16
.
Built-in RAM and control registers for internal peripheral devices are
assigned to bank 0
16
.
Addresses FFD6
16
to FFFF
16
are the RESET and interrupt vector
addresses and contain the interrupt vectors. Use ROM for memory
of this address.
The 2048-byte area allocated to addresses from 80
16
to 87F
16
is the
built-in RAM. In addition to storing data, the RAM is used as stack
during a subroutine call or interrupts.
Peripheral devices such as I/O ports, A-D converter, serial I/O, timer,
and interrupt control registers are allocated to addresses from 0
16
to
7F
16
.
A 256-byte direct page area can be allocated anywhere in bank 0
16
by using the direct page register (DPR). In the direct page addressing
mode, the memory in the direct page area can be accessed with two
words. Hence program steps can be reduced.
000000
16
Bank 0
16
00FFFF
16
010000
16
000000
16
00007F
16
000080
16
000000
16
Internal peripheral
devices
control registers
refer to Fig. 2 for
detail information
Internal RAM
2048 bytes
00007F
16
Bank 1
16
00FFD6
16
01FFFF
16
•••••••••••••••••••
Interrupt vector table
A-D/UART2 trans./rece.
UART1 transmission
UART1 receive
UART0 transmission
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
00087F
16
FE0000
16
Bank FE
16
FEFFFF
16
FF0000
16
Bank FF
16
FFFFFF
16
00FFD6
16
00FFFF
16
00FFFE
16
Timer A1
Timer A0
INT
2
/Key input
INT
1
INT
0
Watchdog timer
DBC
BRK instruction
Zero divide
RESET
: Internal
: External
Fig. 1 Memory map
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
