HD74LV374A
Octal Edge-Triggered D-type Flip-Flops with 3-state Outputs
REJ03D0332–0200Z
(Previous ADE-205-275 (Z))
Rev.2.00
Jun. 25, 2004
Description
The HD74LV374A has eight edge trigger D type flip flops with three state outputs in a 20 pin package. Data at the D
inputs meeting set up requirements, are transferred to the Q outputs on positive going transitions of the clock input.
When the clock input goes low, data at the D inputs will be retained at the outputs until clock input returns high again.
When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of
what signals are present at the other inputs and the state of the storage elements. Low-voltage and high-speed operation
is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the
battery life.
Features
•
•
•
•
•
•
•
V
CC
= 2.0 V to 5.5 V operation
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25°C)
Typical V
OH
undershoot > 2.3 V (@V
CC
= 3.3 V, Ta = 25°C)
Output current ±8 mA (@V
CC
= 3.0 V to 3.6 V), ±16 mA (@V
CC
= 4.5 V to 5.5 V)
Ordering Information
Package Type
SOP–20 pin (JEITA)
SOP–20 pin (JEDEC)
TSSOP–20 pin
Package Code
FP–20DAV
FP–20DBV
TTP–20DAV
Package
Abbreviation
FP
RP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
ELL (2,000 pcs/reel)
Part Name
HD74LV374AFPEL
HD74LV374ARPEL
HD74LV374ATELL
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
OE
H
L
L
L
CLK
X
↑
↑
↓
D
X
L
H
X
Output Q
Z
L
H
Q
0
Note: H: High level
L: Low level
X: Immaterial
Z: High impedance
Q
0
: Output level before the indicated steady state input conditions were established.
Rev.2.00 Jun. 25, 2004, page 1 of 9
HD74LV374A
Pin Arrangement
OE
1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D 7
4D 8
4Q 9
GND 10
20 V
CC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 CLK
(Top view)
Absolute Maximum Ratings
Item
Supply voltage range
Input voltage range*
1
Output voltage range*
1, 2
Input clamp current
Output clamp current
Continuous output current
Continuous current through
V
CC
or GND
Maximum power dissipation at
3
Ta = 25°C (in still air)*
Storage temperature
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
or I
GND
P
T
Tstg
Ratings
–0.5 to 7.0
–0.5 to 7.0
–0.5 to V
CC
+ 0.5
–0.5 to 7.0
–20
±50
±35
±70
835
757
–65 to 150
Unit
V
V
V
mA
mA
mA
mA
mW
°C
Conditions
Output: H or L
V
CC
: OFF or Output: Z
V
I
< 0
V
O
< 0 or V
O
> V
CC
V
O
= 0 to V
CC
SOP
TSSOP
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are
observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Rev.2.00 Jun. 25, 2004 page 2 of 9
HD74LV374A
Recommended Operating Conditions
Item
Supply voltage range
Input voltage range
Output voltage range
Output current
Symbol
V
CC
V
I
V
O
I
OH
Min
2.0
0
0
0
—
—
—
—
—
—
—
—
0
0
0
–40
Max
5.5
5.5
V
CC
5.5
–50
–2
–8
–16
50
2
8
16
200
100
20
85
Unit
V
V
V
µA
mA
Conditions
I
OL
µA
mA
Input transition rise or fall rate
∆t
/∆v
ns/V
H or L
High impedance state
V
CC
= 2.0 V
V
CC
= 2.3 to 2.7 V
V
CC
= 3.0 to 3.6 V
V
CC
= 4.5 to 5.5 V
V
CC
= 2.0 V
V
CC
= 2.3 to 2.7 V
V
CC
= 3.0 to 3.6 V
V
CC
= 4.5 to 5.5 V
V
CC
= 2.3 to 2.7 V
V
CC
= 3.0 to 3.6 V
V
CC
= 4.5 to 5.5 V
Operating free-air temperature
Ta
°C
Note: Unused or floating inputs must be held high or low.
Logic Diagram
OE
CLK
1
11
C1
1D
3
2
1Q
1D
To Seven Other Channels
Rev.2.00 Jun. 25, 2004 page 3 of 9
HD74LV374A
DC Electrical Characteristics
Ta = –40 to 85°C
Item
Input voltage
Symbol
V
IH
V
CC
(V)*
2.0
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
2.0
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
Min to Max
2.3
3.0
4.5
Min to Max
2.3
3.0
4.5
0 to 5.5
5.5
5.5
0
3.3
Min
1.5
V
CC
×
0.7
V
CC
×
0.7
V
CC
×
0.7
—
—
—
—
V
CC
– 0.1
2.0
2.48
3.8
—
—
—
—
—
—
—
—
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.9
Max
—
—
—
—
0.5
V
CC
×
0.3
V
CC
×
0.3
V
CC
×
0.3
—
—
—
—
0.1
0.4
0.44
0.55
±1
±5
20
5
—
Unit
V
Test Conditions
V
IL
Output voltage
V
OH
V
V
OL
Input current
Off-state output
current
Quiescent supply
current
Output leakage
current
Input capacitance
I
IN
I
OZ
I
CC
I
OFF
C
IN
µA
µA
µA
µA
pF
I
OH
= –50
µA
I
OH
= –2 mA
I
OH
= –8 mA
I
OH
= –16 mA
I
OL
= 50
µA
I
OL
= 2 mA
I
OL
= 8 mA
I
OL
= 16 mA
V
IN
= 5.5 V or GND
V
O
= V
CC
or GND
V
IN
= V
CC
or GND, I
O
= 0
V
I
or V
O
= 0 to 5.5 V
V
I
= V
CC
or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Rev.2.00 Jun. 25, 2004 page 4 of 9
HD74LV374A
Switching Characteristics
V
CC
= 2.5 ± 0.2 V
Ta = 25°C
Item
Maximum clock
frequency
Propagation
delay time
Enable time
Disable time
Setup time
Hold time
Pulse width
Symbol
t
max
t
PLH
t
PHL
t
ZH
t
ZL
t
HZ
t
LZ
t
SU
t
h
t
w
Min
60
50
—
—
—
—
—
—
5.0
2.5
6.0
Typ
105
85
9.7
11.8
8.9
10.9
6.3
8.2
—
—
—
Max
—
—
16.3
19.3
15.9
18.8
12.6
17.3
—
—
—
Ta = –40 to 85°C
Min
50
40
1.0
1.0
1.0
1.0
1.0
1.0
5.5
2.5
7.0
Max
—
—
19.0
23.0
19.0
22.0
15.0
19.0
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
Test
Conditions
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
FROM
(Input)
TO
(Output)
CLK
OE
OE
Q
Q
Q
Data before CLK
↑
Data after CLK
↑
CLK: "H" or "L"
V
CC
= 3.3 ± 0.3 V
Ta = 25°C
Item
Maximum clock
frequency
Propagation
delay time
Enable time
Disable time
Setup time
Hold time
Pulse width
Symbol
t
max
t
PLH
t
PHL
t
ZH
t
ZL
t
HZ
t
LZ
t
SU
t
h
t
w
Min
80
55
—
—
—
—
—
—
4.5
2.0
5.0
Typ
150
110
6.8
8.3
6.3
7.7
4.7
5.9
—
—
—
Max
—
—
12.7
16.2
11.0
14.5
10.5
14.0
—
—
—
Ta = –40 to 85°C
Min
70
50
1.0
1.0
1.0
1.0
1.0
1.0
4.5
2.0
5.5
Max
—
—
15.0
18.5
13.0
16.5
12.5
16.0
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
Test
Conditions
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
FROM
(Input)
TO
(Output)
CLK
OE
OE
Q
Q
Q
Data before CLK
↑
Data after CLK
↑
CLK: "H" or "L"
V
CC
= 5.0 ± 0.5 V
Ta = 25°C
Item
Maximum clock
frequency
Propagation
delay time
Enable time
Disable time
Setup time
Hold time
Pulse width
Symbol
t
max
t
PLH
t
PHL
t
ZH
t
ZL
t
HZ
t
LZ
t
SU
t
h
t
w
Min
130
85
—
—
—
—
—
—
3.0
2.0
5.0
Typ
205
170
4.9
5.9
4.6
5.5
3.4
4.0
—
—
—
Max
—
—
8.1
10.1
7.6
9.6
6.8
8.8
—
—
—
Ta = –40 to 85°C
Min
110
75
1.0
1.0
1.0
1.0
1.0
1.0
3.0
2.0
5.0
Max
—
—
9.5
11.5
9.0
11.0
8.0
10.0
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
Test
Conditions
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
FROM
(Input)
TO
(Output)
CLK
OE
OE
Q
Q
Q
Data before CLK
↑
Data after CLK
↑
CLK: "H" or "L"
Rev.2.00 Jun. 25, 2004 page 5 of 9
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