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74HCT14
Hex Schmitt−Trigger
Inverter with LSTTL
Compatible Inputs
High−Performance Silicon−Gate CMOS
The 74HCT14 may be used as a level converter for interfacing TTL
or NMOS outputs to high−speed CMOS inputs.
The HCT14 is useful to “square up” slow input rise and fall times.
Due to the hysteresis voltage of the Schmitt trigger, the HCT14 finds
applications in noisy environments.
Features
14
1
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MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
1
HCT14G
AWLYWW
•
•
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
TTL/NMOS−Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0
mA
In Compliance With the JEDEC Standard No. 7A Requirements
ESD Performance: HBM
>
2000 V; Machine Model
>
200 V
Chip Complexity: 72 FETs or 18 Equivalent Gates
These are Pb−Free Devices
14
14
1
TSSOP−14
DT SUFFIX
CASE 948G
1
HCT
14
ALYW
G
G
HCT14 = Device Code
A
= Assembly Location
L, WL
= Wafer Lot
Y
= Year
W, WW = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2007
March, 2007
−
Rev. 1
1
Publication Order Number:
74HCT14/D
74HCT14
PIN ASSIGNMENT
A1
Y1
A2
Y2
A3
Y3
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
A6
Y6
A5
Y5
A4
Y4
A4
9
8
Y4
A3
5
6
Y3
A2
LOGIC DIAGRAM
A1
1
2
Y1
3
4
Y2
FUNCTION TABLE
Input
A
L
H
Output
Y
H
L
A5
11
10
Y5
A6
13
12
Y6
Y=A
PIN 14 = V
CC
PIN 7 = GND
ORDERING INFORMATION
Device
74HCT14DR2G
74HCT14DTR2G
Package
SOIC−14
(Pb−Free)
TSSOP−14*
Shipping
†
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
74HCT14
MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
T
L
T
J
q
JA
P
D
MSL
F
R
V
ESD
I
Latchup
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
Power Dissipation in Still Air at 85_C
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Latchup Performance
Oxygen Index: 30%
−
35%
Human Body Model (Note 1)
Machine Model (Note 2)
Above V
CC
and Below GND at 85_C (Note 3)
SOIC
TSSOP
SOIC
TSSOP
Parameter
(Referenced to GND)
(Referenced to GND)
(Referenced to GND)
Value
*0.5
to
)7.0
*0.5
to V
CC
)0.5
*0.5
to V
CC
)0.5
$20
$25
$25
$50
$50
*65
to
)150
260
)150
125
170
500
450
Level 1
UL 94 V−0 @ 0.125 in
>2000
>200
$300
V
mA
Unit
V
V
V
mA
mA
mA
mA
mA
_C
_C
_C
_C/W
mW
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to EIA/JESD78.
4. For high frequency or heavy load considerations, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
, V
O
T
A
t
r
, t
f
DC Supply Voltage
DC Input Voltage, Output Voltage
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
Parameter
(Referenced to GND)
(Referenced to GND)
Min
4.5
0
*55
−
Max
5.5
V
CC
)125
(Note 5)
Unit
V
V
_C
ns
5. No Limit when V
I
[
50% V
CC
, I
CC
> 1 mA.
6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
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3
74HCT14
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Temperature Limit
V
CC
Symbol
V
T)
max
V
T)
min
V
T*
max
V
T*
min
V
H
max
V
H
min
V
OH
Parameter
Maximum Positive−Going
Input Threshold Voltage
Minimum Positive−Going
Input Threshold Voltage
Maximum Negative−Going
Input Threshold Voltage
Minimum Negative−Going
Input Threshold Voltage
Maximum Hysteresis
Voltage
Minimum Hysteresis
Voltage
Minimum High−Level
Output Voltage
Test Conditions
V
O
= 0.1 V or V
CC
– 0.1 V
|I
out
|
v
20
mA
V
O
= 0.1 V or V
CC
– 0.1 V
|I
out
|
v
20
mA
V
O
= 0.1 V or V
CC
– 0.1 V
|I
out
|
v
20
mA
V
O
= 0.1 V or V
CC
– 0.1 V
|I
out
|
v
20
mA
V
O
= 0.1 V or V
CC
– 0.1 V
|I
out
|
v
20
mA
V
O
= 0.1 V or V
CC
– 0.1 V
|I
out
|
v
20
mA
V
I
< V
T*
min
|I
out
|
v
20
mA
V
I
< V
T*
min
|I
out
|
v
4.0 mA
V
OL
Maximum Low−Level
Output Voltage
V
I
≥
V
T)
max
|I
out
|
v
20
mA
V
I
≥
V
T)
max
|I
out
|
v
4.0 mA
I
IK
I
CC
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
(per package)
V
I
= V
CC
or GND
V
I
= V
CC
or GND
I
out
= 0
mA
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
4.5
5.5
4.5
5.5
5.5
0.4
0.4
4.4
5.4
3.98
0.1
0.1
0.26
$0.1
2.0
0.5
0.6
1.4
1.5
0.4
0.4
4.4
5.4
3.84
0.1
0.1
0.33
$1.0
20
1.2
1.4
1.2
1.4
0.5
0.6
1.4
1.5
0.4
04
4.4
5.4
3.7
0.1
0.1
0.4
$1.0
40
mA
mA
V
V
*55_C
to 25_C
Min
Max
1.9
2.1
1.2
1.4
1.2
1.4
0.5
0.6
1.4
1.5
v85_C
Min
Max
1.9
2.1
1.2
1.4
1.2
1.4
v125_C
Min
Max
1.9
2.1
Unit
V
V
w*55_C
DI
CC
Additional Quiescent
Supply Current
V
I
= 2.4 V, Any One Input
V
I
= V
CC
or GND, Other Inputs
l
out
= 0
mA
5.5
2.9
25_C to 125_C
2.4
mA
7. Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS
(C
L
= 50 pF; Input t
r
= t
f
= 6.0 ns)
Guaranteed Limit
*55_C
to 25_C
Symbol
Parameter
Test Conditions
Figures
Min
Max
v85_C
Min
Max
v125_C
Min
Max
Unit
t
PLH
,
t
PHL
t
TLH
,
t
THL
Maximum Propagation
Delay, Input A to Output
Y (L to H)
Maximum Output
Transition Time, Any
Output
V
CC
= 5.0 V
$10%
C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns
V
CC
= 5.0 V
$10%
C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns
1&2
32
40
48
ns
1&2
15
19
22
ns
8. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance, per Inverter (Note 9)
32
pF
9. Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
. For load considerations, see the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
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4
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