SN74LS195A
Universal 4-Bit
Shift Register
The SN74LS195A is a high speed 4-Bit Shift Register offering
typical shift frequencies of 39 MHz. It is useful for a wide variety of
register and counting applications. It utilizes the Schottky diode
clamped process to achieve high speeds and is fully compatible with
all ON Semiconductor TTL products.
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•
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Typical Shift Right Frequency of 39 MHz
Asynchronous Master Reset
J, K Inputs to First Stage
Fully Synchronous Serial or Parallel Data Transfers
Input Clamp Diodes Limit High Speed Termination Effects
LOW
POWER
SCHOTTKY
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
Parameter
Supply Voltage
Operating Ambient
Temperature Range
Output Current – High
Output Current – Low
Min
4.75
0
Typ
5.0
25
Max
5.25
70
–0.4
8.0
Unit
V
°C
mA
mA
16
1
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device
SN74LS195AN
SN74LS195AD
SN74LS195ADR2
Package
16 Pin DIP
SOIC–16
SOIC–16
Shipping
2000 Units/Box
38 Units/Rail
2500/Tape & Reel
©
Semiconductor Components Industries, LLC, 2001
1
October, 2001 – Rev. 7
Publication Order Number:
SN74LS195A/D
SN74LS195A
CONNECTION DIAGRAM DIP
(TOP VIEW)
VCC
16
Q0
15
Q1
14
Q2
13
Q3
12
Q3
11
CP
10
PE
9
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In Line Package.
1
MR
2
J
3
K
4
P0
5
P1
6
P2
7
P3
8
GND
LOADING
(Note a)
PIN NAMES
PE
P0 - P3
J
K
CP
MR
Q0 - Q3
Q3
Parallel Enable (Active LOW) Input
Parallel Data Inputs
First Stage J (Active HIGH) Input
First Stage K (Active LOW) Input
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Parallel Outputs
Complementary Last Stage Output
HIGH
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
mA
HIGH/1.6 mA LOW.
LOGIC SYMBOL
9
4
5
6
7
2
10
3
J
K
PE P0 P1 P2 P3
Q3
11
CP
MR Q0 Q1 Q2 Q3
1 15 14 13 12
VCC = PIN 16
GND = PIN 8
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SN74LS195A
LOGIC DIAGRAM
PE J
9
2
3
K
4
P0
5
P1
6
P2
7
P3
1
MR
10
CP
R CD Q0
CP
S
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
Q0
15
R CD
CP
S
Q0
14
R CD
CP
S
Q2
13
R CD Q3
CP
S
Q3
12
11
Q0
Q1
Q2
Q3 Q3
FUNCTIONAL DESCRIPTION
The Logic Diagram and Truth Table indicate the
functional characteristics of the LS195A 4-Bit Shift
Register. The device is useful in a wide variety of shifting,
counting and storage applications. It performs serial,
parallel, serial to parallel, or parallel to serial data transfers
at very high speeds.
The LS195A has two primary modes of operation, shift
right (Q0
³
Q1) and parallel load which are controlled by the
state of the Parallel Enable (PE) input. When the PE input is
HIGH, serial data enters the first flip-flop Q0 via the J and
K inputs and is shifted one bit in the direction Q0
³
Q1
³
Q2
³
Q3 following each LOW to HIGH clock transition.
The JK inputs provide the flexibility of the JK type input for
special applications, and the simple D type input for general
applications by tying the two pins together. When the PE
input is LOW, the LS195A appears as four common clocked
D flip-flops. The data on the parallel inputs P0, P1, P2, P3 is
transferred to the respective Q0, Q1, Q2, Q3 outputs
following the LOW to HIGH clock transition. Shift left
operations (Q3
³
Q2) can be achieved by tying the Qn
Outputs to the Pn–1 inputs and holding the PE input LOW.
All serial and parallel data transfers are synchronous,
occurring after each LOW to HIGH clock transition. Since
the LS195A utilizes edge-triggering, there is no restriction
on the activity of the J, K, Pn and PE inputs for logic
operation — except for the set-up and release time
requirements.
A LOW on the asynchronous Master Reset (MR) input
sets all Q outputs LOW, independent of any other input
condition.
MODE SELECT — TRUTH TABLE
INPUTS
OPERATING MODES
Asynchronous Reset
Shift, Set First Stage
Shift, Reset First
Shift, Toggle First Stage
Shift, Retain First Stage
Parallel Load
MR
L
H
H
H
H
H
PE
X
h
h
h
h
I
J
X
h
I
h
I
X
K
X
h
I
I
h
X
Pn
X
X
X
X
X
pn
Q0
L
H
L
q0
q0
p0
Q1
L
q0
q0
q0
q0
p1
OUTPUTS
Q2
L
q1
q1
q1
q1
p2
Q3
L
q2
q2
q2
q2
p3
Q3
H
q2
q2
q2
q2
p3
L = LOW voltage levels
H = HIGH voltage levels
X = Don’t Care
I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition.
h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition.
pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to
HIGH clock transition.
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SN74LS195A
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
2.7
–0.65
3.5
0.25
VOL
Output LOW Voltage
0.35
Input HIGH Current
0.1
Input LOW Current
Short Circuit Current (Note 1)
–20
–0.4
–100
0.5
20
IIH
IIL
IOS
V
µA
mA
mA
mA
0.4
Min
2.0
0.8
–1.5
Typ
Max
Unit
V
V
V
V
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = –18 mA
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX
ICC
Power Supply Current
21
mA
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25°C)
Limits
Symbol
fMAX
tPLH
tPHL
tPHL
Parameter
Maximum Clock Frequency
Propagation Delay,
Clock to Output
Propagation Delay,
MR to Output
Min
30
Typ
39
14
17
19
22
26
30
Max
Unit
MHz
ns
ns
VCC = 5.0 V
CL = 15 pF
Test Conditions
AC SETUP REQUIREMENTS
(TA = 25°C)
Limits
Symbol
tW
tW
ts
ts
trec
trel
th
Parameter
CP Clock Pulse Width
MR Pulse Width
PE Setup Time
Data Setup Time
Recovery Time
PE Release Time
Data Hold Time
0
Min
16
12
25
15
25
10
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
VCC = 5.0 V
Test Conditions
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SN74LS195A
DEFINITIONS OF TERMS
SETUP TIME(ts) —is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW to HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time
following the clock transition from LOW to HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
AC WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.
PE
J&K
tW
CLOCK
OUTPUT
tPHL
1.3 V
CONDITIONS: J = PE = MR = H
K=L
1.3 V
1.3 V
tPLH
1.3 V
1.3 V
ts(L)
th(L) = 0
ts(L)
ts(H)
th(H) = 0
1.3 V
ts(H)
th(H) = 0
P0 P1 P2 P3
th(L) = 0
CLOCK
OUTPUT*
1.3 V
CONDITIONS: MR = H
*J AND K SET-UP TIME AFFECTS Q0 ONLY
Figure 1. Clock to Output Delays and
Clock Pulse Width
Figure 3. Setup (ts) and Hold (th) Time for Serial Data
(J & K) and Parallel Data (P0, P1, P2, P3)
MR
tW
1.3 V
1.3 V
trec
PE
LOAD PARALLEL DATA
1.3 V
ts(L)
CLOCK
trel
1.3 V
ts(H)
LOAD SERIAL DATA
SHIFT RIGHT
1.3 V
trel
1.3 V
CLOCK
tPHL
OUTPUT
1.3 V
1.3 V
CONDITIONS: PE = L
PO = P1 = P2 = P3 = H
OUTPUT
Qn = Pn
Qn* = Qn-1
Figure 2. Master Reset Pulse Width, Master Reset
to Output Delay and Master Reset to Clock
Recovery Time
CONDITIONS: MR = H
*Q0 STATE WILL BE DETERMINED BY J AND K INPUTS.
Figure 4. Setup (ts) and Hold (th) Time for PE Input
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