SRAM
Austin Semiconductor, Inc.
128K x 32 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-95595: -Q
• SMD 5962-93187: -P or -PN
• MIL-STD-883
AS8S128K32
PIN ASSIGNMENT
(Top View)
68 Lead CQFP (Q)
FEATURES
• Access times of 15, 17, 20, 25, 35, and 45 ns
• Built in decoupling caps for low noise operation
• Organized as 128K x32; User configured as
256Kx16 or 512K x8
• Operation with single 5 volt supply
• Low power CMOS
• TTL Compatible Inputs and Outputs
• 2V Data Retention, Low power standby
66 Lead PGA- Pins 8, 21, 28, 39 are grounds (P)
OPTIONS
•
Timing
15ns
17ns
20ns
25ns
35ns
45ns
Package
Ceramic Quad Flatpack
Pin Grid Array -8 Series
Pin Grid Array -8 Series
MARKINGS
-15
-17
-20
-25
-35
-45
•
Q
P
PN
No. 702
No. 802
No. 802
66 Lead PGA- Pins 8, 21, 28, 39 are no connects (PN)
NOTE:
PN indicates a no connect on pins 8, 21, 28, 39
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS8S128K32 is a 4 Mega-
bit CMOS SRAM Module organized as 128Kx32-bits and user
configurable to 256Kx16 or 512Kx8. The AS8S128K32 achieves
high speed access, low power consumption and high reliability
by employing advanced CMOS memory technology.
The military temperature grade product is suited for mili-
tary applications.
The AS8S128K32 is offered in a ceramic quad flatpack mod-
ule per SMD-5962-95595 with a maximum height of 0.140 inches.
This module makes use of a low profile, mutlichip module de-
sign.
This device is also offered in a 1.075 inch square ceramic
pin grid array per SMD 5692-93187, which has a maximum height
of 0.195 inches. This package is also a low profile, multi-chip
module design reducing height requirements to a minimum.
CE4
WE4
128K x 8
CE3
WE3
M2
128K x 8
M3
I/O 24 - I/O 31
128K x 8
CE2
WE2
M1
I/O 16 - I/O 23
CE1
WE1
OE
A0 - 16
128K x 8
M0
I/O 8 - I/O 23
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS8S128K32
Rev. 3.5 7/00
I/O 0 - I/O 7
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
SRAM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Voltage of Vcc Supply Relative to Vss.....................-1V to +7V
Storage Temperature..........................................-65°C to +150°C
Short Circuit Output Current(per I/O)...............................20mA
Voltage on Any Pin Relative to Vss..................-.5V to Vcc+1V
Maximum Junction Temperature**.................................+175°C
*Stresses greater than those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
AS8S128K32
This is a stress rating only and functional operation on the
device at these or any other conditions above those indicated
in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
**Junction temperature depends upon package type, cycle time,
loading, ambient temperature and airflow. See the Application
Information section at the end of this datasheet for more infor-
mation.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55°C<TA<125°C; Vcc = 5v ±10%)
''" !
''" !
µΑ
µΑ
µΑ
( )
)
( )
)
(
(* * +*,-
( )
)
. /0#
. 0#
12
/
/
/
PARAMETER
Power Supply Current:
Operating
CONDITIONS
CE\<V
IL
; V
CC
=MAX
f = MAX = 1/t
RC
(MIN)
Outputs Open
CE\>V
IH
; V
CC
=MAX
f = MAX = 1/t
RC
(MIN)
Outputs Open
CE\ = OE\ = V
IH
;
CMOS Compatible; V
CC
= MAX
f = 5 MHz
SYM
I
cc
-15
700
-17
650
MAX
-20
-25
600
560
-35
520
-45
500
UNITS NOTES
mA
3, 13
(1)
I
SBT1
280
220
200
180
160
150
mA
(1)
I
SBT2
100
80
80
60
60
60
mA
(1)
Power Supply Current:
Standby
CE\ > V
cc
-0.2V; Vcc = MAX
V
IL
< V
ss
+0.2V;
V
IH
> V
CC
-0.2V; f = 0 Hz
CE\ > Vcc -0.2V; Vcc = MAX
V
IL
< Vss +0.2V;
V
IH
> Vcc -0.2V; f = 0 Hz
"L" Version Only
I
SBC1
40
40
40
40
40
40
mA
(2)
I
SBC2
24
24
24
24
24
24
mA
(2)
NOTE:
1) Address switching sequence A, A+1, A+2, etc.
2) 1/2 input at HIGH, 1/2 input at LOW.
AS8S128K32
Rev. 3.5 7/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
SRAM
Austin Semiconductor, Inc.
CAPACITANCE TABLE
(V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C)
SYMBOL
C
ADD
C
OE
C
WE,
C
CE
C
IO
PARAMETER
A0 - A18 Capacitance
OE\ Capacitance
WE\ and CE\ Capacitance
I/O 0- I/O 31 Capacitance
MAX
40
40
20
20
UNITS
pF
pF
pF
pF
NOTES
4
4
4
4
AS8S128K32
TRUTH TABLE
MODE
Read
Write
Standby
Not Selected
OE\
L
X
X
H
CE\
L
L
H
L
WE\
H
L
X
H
I/O
Q
D
HIGH Z
HIGH Z
POWER
ACTIVE
ACTIVE
STANDBY
ACTIVE
AC TEST CONDITIONS
TEST SPECIFICATIONS
Input pulse levels........................................VSS to 3V
Input rise and fall times..........................................5ns
Input timing reference levels.................................1.5V
Output reference levels........................................1.5V
Output load.............................................See Figures 1
Vz = 1.5V
(Bipolar
Supply)
I
OL
Current Source
Device
Under
Test
-
+
+
Ceff = 50pf
Current Source
I
OH
NOTES:
Vz is programable from -2V to + 7V.
I
OL
and I
OH
programmable from 0 to 16 mA.
Vz is typically the midpoint of V
OH
and V
OL
.
I
OL
and I
OH
are adjusted to simulate a typical resistive load
circuit.
Figure 1
AS8S128K32
Rev. 3.5 7/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
SRAM
Austin Semiconductor, Inc.
AS8S128K32
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55
°C≤TA≤125°C; Vcc = 5v ±10%)
DESCRIPTION
READ CYCLE
READ cycle time
Address access time
Chip enable access time
Output hold from address change
Chip enable to output in Low-Z
Chip disable to output in High-Z
Chip enable to power-up time
Chip disable to power-down time
Output enable access time
Output enable to output in Low-Z
Output disable to output in High-Z
WRITE CYCLE
WRITE cycle time
Chip enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
WRITE pulse width
WRITE pulse width
Data setup time
Data hold time
Write disable to output in Low-z
Write enable to output in High-Z
-15
-17
-20
-25
-35
-45
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
RC
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
PU
t
PD
t
AOE
t
LZOE
t
HZOE
t
t
t
t
15
15
15
2
2
7
0
15
6
0
6
15
12
12
0
1
12
12
8
1
2
1
1
17
17
17
2
2
8
0
17
7
0
7
17
12
12
0
1
12
12
9
1
2
7
1
1
20
20
20
2
2
9
0
20
7
0
7
20
15
15
0
1
15
15
10
1
2
9
10
25
25
25
2
2
10
0
25
8
0
9
25
17
17
0
1
17
17
12
1
2
11
35
35
35
2
2
14
0
35
12
0
12
35
20
20
0
1
20
20
15
1
2
14
45
45
45
2
2
15
0
45
12
0
12
45
22
22
0
1
20
20
15
1
2
15
ns
ns
ns
ns
ns
ns
4, 6, 7
4, 6, 7
4
4
4, 6
4, 6, 7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CW
t
AW
t
AS
t
AH
t
t
WP1
WP2
t
DS
t
DH
t
LZWE
t
HZWE
4, 6, 7
4, 6, 7
NOTES:
1) For OE\ = HIGH condition. For OE\ = LOW condition
t
WP1 =
t
WP2 = 15 ns MIN.
AS8S128K32
Rev. 3.5 7/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SRAM
Austin Semiconductor, Inc.
NOTES
1. All voltages referenced to V
SS
(GND).
2. -3v for pulse width <20ns.
3. I
CC
is dependent on output loading and cycle rates.
The specified value applies with the outputs
1
open, and f=
H
Z.
t
RC(MIN)
4. This parameter is sampled.
5. Test conditions as specified with output loading as
shown in Fig. 1 unless otherwise noted.
6. t
HZCE
, t
HZOE
and t
HZWE
are specified with C
L
= 5pF
as in Fig. 2. Transition is measured +/- 200 mV
typical from steady state coltage, allowing for actual
tester RC time constant.
7. At any given temperature and voltage condition,
t
HZCE
, is less than t
LZCE
, and t
HZWE
is less than t
LZWE
.
8.
?
W
/
E is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and output
enable are held in their active state.
10. Address valid prior to or coincident with latest occurring
chip enable.
11. t
RC
= READ cycle time.
12. Chip enable (?C
/
E) and write enable (?WE) can initiate and
/
terminate a WRITE cycle.
13. 32 bit operation
AS8S128K32
DATA RETENTION ELECTRICAL CHARACTERISTICS
DESCRIPTION
V
CC
for Retention Data
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
CONDITIONS
CE\ > V
CC
- 0.2V
V
IN
> V
CC
- 0.2V
V
CC
= 2.0V
V
CC
= 3V
SYMBOL
V
DR
I
CCDR
I
CCDR
t
CDR
t
R
MIN
2
--
--
0
t
RC
MAX
--
6
11.6
--
UNITS
V
mA
mA
ns
ns
4
4, 11
NOTES
LOW V
CC
DATA RETENTION WAVEFORM
DATA RETENTION MODE
VDR
>2V
Vcc
tCDR
V
IH
4.5V
4.5V
tR
VDR
CE\
V
IL
AS8S128K32
Rev. 3.5 7/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
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