Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Commercial
Ambient
Temperature
0
°
C to +70
°
C
V
CC
3.3V
±
300mV
Pin Definitions
Signal Name
D
0
−
8
Q
0
−
8
WEN1
Description
Data Inputs
Data Outputs
Write Enable 1
I/O
I
O
I
Data Inputs for 9-bit bus
Data Outputs for 9-bit bus
The only write enable when device is configured to have programmable flags. Data is
written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH.
If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH transition
of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin
operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO
if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW
to write or read the programmable flag offsets.
Enables the device for Read operation.
The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH
and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-off-
set register.
Description
WEN2/LD
Dual Mode Pin
Write Enable 2
Load
I
I
REN1, REN2
WCLK
Read Enable
Inputs
Write Clock
I
I
2
PRELIMINARY
Pin Definitions
(continued)
Signal Name
RCLK
Description
Read Clock
I/O
I
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Description
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the FIFO
is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag-offset
register.
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value pro-
grammed into the FIFO.
When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed
into the FIFO.
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is
HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
EF
FF
PAE
PAF
RS
OE
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Reset
Output Enable
O
O
O
O
I
I
Electrical Characteristics
Over the Operating Range
[1]
7C42X1V-15
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZL
I
OZH
I
CC[2]
I
SB[3]
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Current
Output OFF,
High Z Current
Active Power Supply
Current
Average Standby
Current
V
CC
= Max.
OE > V
IH
,
V
SS
< V
O
< V
CC
Com’l
Com’l
Test Conditions
V
CC
= Min.,
I
OH
=
−2.0
mA
V
CC
= Min.,
I
OL
= 8.0 mA
2.0
−0.5
−10
−10
Min.
2.4
0.4
5.0
0.8
+10
+10
20
6
2.0
−0.5
−10
−10
Max.
7C42X1V-25
Min.
2.4
0.4
5.0
0.8
+10
+10
20
6
2.0
−0.5
−10
−10
Max.
7C42X1V- 35
Min.
2.4
0.4
5.0
0.8
+10
+10
20
6
Max.
Unit
V
V
V
V
µA
µA
mA
mA
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 5.0V
Max.
5
7
Unit
pF
pF
3
PRELIMINARY
AC Test Loads and Waveforms
[5, 6]
R1= 330 Ohms
3.3V
OUTPUT
C
L
INCLUDING
JIG AND
SCOPE
Equivalent to:
R2=510 Ohms
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
ALL INPUT PULSES
3.0V
GND
≤
3 ns
90%
10%
90%
10%
≤
3 ns
42X1V–5
42X1V–4
THÉ VENIN EQUIVALENT
Rth=200 Ohms
OUTPUT
Vth=2.0V
Switching Characteristics
Over the Operating Range
7C42X1V-15
Parameter
t
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
PAF
t
PAE
t
SKEW1
t
SKEW2
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Set-Up Time
Data Hold Time
Enable Set-Up Time
Enable Hold Time
Reset Pulse Width
[7]
Reset Set-Up Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low Z
[8]
Output Enable to Output Valid
Output Enable to Output in High Z
[8]
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Programmable Almost-Full Flag
Clock to Programmable Almost-Full Flag
Skew Time between Read Clock and Write Clock
for Empty Flag and Full Flag
Skew Time between Read Clock and Write Clock
for Almost-Empty Flag and Almost-Full Flag
6
15
0
3
3
8
8
11
11
11
11
10
18
Description
Clock Cycle Frequency
2
15
6
6
4
1
4
1
15
10
10
15
0
3
3
12
12
15
15
15
15
12
20
Min.
Max.
66.7
11
2
25
10
10
6
2
6
2
25
15
15
25
0
3
3
15
15
20
20
20
20
7C42X1V-25
Min.
Max.
40
15
2
35
14
14
7
2
7
2
35
20
20
35
7C42X1V-35
Min.
Max.
28.6
20
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. See the last page of this specification for Group A subgroup testing information.
2. Outputs open. Tested at Frequency = 20 MHz.
3. All inputs = V
CC
- 0.2V, except WCLK and RCLK, which are switching at 20MHz.
4. Tested initially and after any design or process changes that may affect these parameters.
5. C
L
= 30 pF for all AC parameters except for t
OHZ
.
6. C
L
= 5 pF for t
OHZ
.
7. Pulse widths less than minimum values are not allowed.
8. Values guaranteed by design, not currently tested.
4
PRELIMINARY
Switching Waveforms
Write Cycle Timing
t
CLKH
WCLK
t
DS
D
0
–D
8
t
ENS
WEN1
t
CLK
t
CLKL
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
t
DH
t
ENH
NO OPERATION
WEN2
(if applicable)
FF
t
SKEW1
RCLK
[9]
NO OPERATION
t
WFF
t
WFF
REN1,REN2
42X1V–6
Read Cycle Timing
t
CLKH
RCLK
t
ENS
REN1,REN2
t
REF
EF
t
A
Q
0
–Q
8
t
OLZ
t
OE
OE
t
ENH
t
CKL
t
CLKL
NO OPERATION
t
REF
VALID DATA
t
OHZ
t
SKEW1
WCLK
[10]
WEN1
WEN2
42X1V–7
Notes:
9. t
SKEW1
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the
rising edge of RCLK and the rising edge of WCLK is less than t
SKEW1
, then FF may not change state until the next WCLK rising edge.
10. t
SKEW1
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the
rising edge of WCLK and the rising edge of RCLK is less than t
SKEW1
, then EF may not change state until the next RCLK rising edge.
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