Product Brief
FW321 07 NV129
1394a PCI PHY/Link Open Host Controller Interface
Mixed-Format Codecs for Non-Linear Editing,
F e at u r e s
n
129-ball VTFSBGA lead-free package.
1394a-2000 OHCI link and PHY core
function in a single device:
— Single-chip link and PHY enable
smaller, simpler, more efficient
motherboard and add-in card designs.
— Compatibility with current
Microsoft Windows® drivers and
common applications.
— Interoperability with existing, as well
as older, 1394 consumer electronics
and peripherals products.
— Support low-power system designs
(CMOS implementation and power
management features).
— LPS, LKON, and CNA outputs to
support legacy power management
implementations.
— 2 Kbyte asynchronous receive FIFO.
— Dedicated asynchronous and
isochronous descriptor-based DMA
engines.
— Eight isochronous transmit/receive
contexts.
— Prefetches isochronous transmit data.
— Supports posted write transactions.
— Supports parallel processing of incoming
physical read and write requests.
— May be used without an EEPROM when
the system BIOS is programmed with the
EEPROM contents.
n
n
PCI:
— Revision 2.3 compliant.
— 33 MHz/32-bit operation.
— Programmable burst size thresholds for
PCI data transfer.
— Supports optimized memory read line,
memory read multiple, and memory
write invalidate burst commands.
— Supports PCI Bus Power Management
Interface Specification v.1.1.
— Supports CLKRUN# protocol per PCI
Mobile Design Guide.
— Supports Mini PCI Specification v1.0,
including Mini PCI ® power requirements.
— CardBus support per PC card standard
release 8.0, including 128 bytes of on-chip
tuple memory.
n
1394a-2000 PHY core:
— Compliant with IEEE ® 1394a-2000,
Standard for a High Performance Serial
Bus.
— Provides one fully compliant cable port,
supporting 400 Mbits/s, 200 Mbits/s, and
100 Mbits/s traffic.
— Does not require external filter capacitor
for PLL.
— Supports link-on as a part of the internal
PHY core-link interface.
— Supports arbitrated short bus reset to
improve utilization of the bus.
— Supports multispeed packet
concatenation.
— Supports PHY pinging and remote PHY
access packets.
— Reports cable power fail interrupt when
voltage at CPS pin falls below 7.5 V.
n
OHCI:
— Complies with the 1394 OHCI 1.1
Specification.
— OHCI 1.0 backwards compatible:
configurable via PCI bus commands
to operate in either OHCI 1.0 or
Other Features
n
CMOS process.
3.3 V operation, 5 V tolerant inputs.
I2C serial ROM interface.
n
n
n
OHCI 1.1 mode.
— Listed on Windows hardware
compatibility list http://tested
products.windowsmarketplace.com.
— Compatible with Microsoft Windows
and MacOS® operating systems.
— 4 Kbyte isochronous transmit FIFO.
— 2 Kbyte asynchronous transmit FIFO.
— 4 Kbyte isochronous receive FIFO.
Functional Block Diagram
ASYNCHRONOUS
DATA
TRANSFER
PCI
BUS
PCI
CORE
OHCI
ISOCHRONOUS
DATA
TRANSFER
LINK
CORE
PHY
CORE
CABLE
PORT 0
ROM I/F
O r d e r i n g i n F O r m at i O n :
Device
L-FW321-076-NV129-DB*†
Comcode
711009132
Package
129-Ball VTFSBGAC
* Lead-free: No intentional addition of lead, and less than 1000 ppm.
† LSI lead-free devices are fully compliant with the Restriction of Hazardous Substances (RoHS)
directive that restricts the content of six hazardous substances in electronic equipment in the
European Union. Beginning July 1, 2006, electronic equipment sold in the European Union
must be manufactured in accordance with the standards set by the RoHS directive.
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lsi.com lsi.com/contacts
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products and services herein at any time without notice. LSI does not assume any responsibility or liability arising out of the application or use
of any product or service described herein, except as expressly agreed to in writing by LSI; nor does the purchase, lease, or use of a product or
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of third parties.
Copyright ©2006 by LSI Corporation. All rights reserved.
June 2006
PB06-028CMPR
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