CAT24C00
128-Bit Serial EEPROM
FEATURES
I
400 kHz I
2
C bus compatible*
I
1.8 to 5.5 volt operation
I
Low power CMOS technology
I
Self-timed write cycle with auto-clear
I
1,000,000 Program/erase cycles
I
100 year data retention
I
8-pin DIP, 8-pin SOIC, 8 pin TSSOP and SOT-23
I
Industrial and Extended Temperature Ranges
DESCRIPTION
The CAT24C00 is a 128-bit Serial CMOS EEPROM
internally organized as 16 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces
device power requirements. The device operates via the
I
2
C bus serial interface and is available in 8-pin DIP,
8-pin SOIC, 8-pin TSSOP and 5-pin SOT-23.
PIN CONFIGURATION
DIP Package (P, L, GL)
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VCC
NC
SCL
SDA
SOIC Package (J, W, GW)
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
SOT-23 (TP, TB, GTB)
SCL
VSS
SDA
1
2
5
VCC
TSSOP Package (U, Y, GY)
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
PIN FUNCTIONS
Pin Name
SDA
SCL
NC
i
D
3
4
c
s
NC
n
o
i
t
VCC
NC
SCL
SDA
u
n
VCC
VSS
SDA
BLOCK
DIAGRAM
EXTERNAL LOAD
d
e
a
P
t
r
DOUT
ACK
SENSE AMPS
SHIFT REGISTERS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
VCC
NC
SCL
SDA
START/STOP
LOGIC
XDEC
CONTROL
LOGIC
E
2
PROM
Function
DATA IN STORAGE
Serial Data/Address
HIGH VOLTAGE/
TIMING CONTROL
SCL
STATE COUNTERS
Serial Clock
No Connect
1.8 V to 5.5 V Power Supply
Ground
V
CC
V
SS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1027, Rev. O
CAT24C00
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
............ –2.0 V to V
CC
+ 2.0 V
V
CC
with Respect to Ground ............. –2.0 V to +7.0 V
Package Power Dissipation
Capability (T
A
= 25°C) .................................. 1.0 W
Lead Soldering Temperature (10 seconds) ...... 300°C
Output Short Circuit Current
(2)
....................... 100 mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Typ.
Max.
1,000,000
100
2000
100
D.C. OPERATING CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, unless otherwise specified.
Symbol
I
CC
I
SB(5)
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OL2
Parameter
Power Supply Current
Test Conditions
Standby Current (V
CC
= 5.0 V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5 V
Symbol
C
I/O(3)
C
IN(3)
Parameter
Test Conditions
V
I/O
= 0 V
V
IN
= 0 V
Min
Typ
Max
8
6
Units
pF
pF
Input/Output Capacitance (SDA)
Input Capacitance (SCL)
Note:
(1) The minimum DC input voltage is – 0.5 V. During transitions, inputs may undershoot to – 2.0 V for periods of less than 20 ns. Maximum
DC voltage on output pins is V
CC
+ 0.5 V, which may overshoot to V
CC
+ 2.0 V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from – 1 V to V
CC
+ 1 V.
(5) Maximum standby current (I
SB
) = 10µA for the Extended Automotive temperature range.
i
D
Output Low Voltage (V
CC
= 3.0 V)
Output Low Voltage (V
CC
= 1.8 V)
c
s
n
o
V
IN
= GND or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
–1
V
CC
x 0.7
I
OL
= 3 mA
I
OL
= 1.5 mA
i
t
f
SCL
= 400 kHz
u
n
d
e
Min
a
P
Max
2
1
10
10
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.5
Units
Cycles/Byte
Years
Volts
mA
t
r
mA
µA
µA
µA
V
V
V
V
Typ
Units
Doc. No. 1027, Rev. O
2
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C00
A.C. CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
1.8 V - 6.0 V
Min
F
SCL
T
I(1)
t
AA
t
BUF(1)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(1)
t
F(1)
t
SU:STO
t
DH
Clock Frequency
Noise Suppression Time
Constant at SCL, SDA Inputs
SCL Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
4.7
4
4.7
4
Max
100
100
3.5
1.2
2.5 V - 6.0 V
Min
Max
400
100
Units
Stop Condition Setup Time
Data Out Hold Time
Power-Up Timing
(1)(2)
Symbol
t
PUR
t
PUW
Write Cycle Limits
Symbol
t
WR
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
i
D
c
s
Parameter
Parameter
Power-up to Read Operation
Power-up to Write Operation
n
o
i
t
u
n
0
50
4
100
4.7
d
e
1.2
0.6
0.6
0
50
1
300
0.6
100
Min
Typ
0.6
a
P
1
0.3
300
Max
1
1
t
r
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
Units
ms
ms
Min
Typ
Max
5
Units
ms
Write Cycle Time
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1027, Rev. O
CAT24C00
FUNCTIONAL DESCRIPTION
The CAT24C00 supports the I
2
C Bus data transmission
protocol. This Inter-Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. Data
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditions for bus access. The CAT24C00 operates as
a Slave device. Both the Master and Slave devices can
operate as either transmitter or receiver, but the Master
device controls which mode is activated.
SDA:
Serial Data/Address
The CAT24C00 bidirectional serial data/address pin is
used to transfer data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
I
2
C BUS PROTOCOL
The following defines the features of the I
2
C bus protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
PIN DESCRIPTIONS
SCL:
Serial Clock
The CAT24C00 serial clock input pin is used to clock all
data transfers into or out of the device. This is an input
pin.
Figure 1. Bus Timing
tF
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tHIGH
tLOW
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
tR
SDA IN
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
Figure 3. Start/Stop Timing
i
D
c
s
8TH BIT
BYTE n
SDA
SCL
n
o
ACK
tAA
i
t
u
n
tSU:DAT
tDH
tWR
d
e
a
P
t
r
tSU:STO
tBUF
5020 FHD F03
STOP
CONDITION
START
CONDITION
ADDRESS
5020 FHD F04
5020 FHD F05
START BIT
Doc. No. 1027, Rev. O
STOP BIT
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C00
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24C00 monitors the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
The CAT24C00 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
When the CAT24C00 is in a READ mode it transmits 8
bits of data, releases the SDA line, and monitors the line
for an acknowledge. Once it receives this acknowledge,
the CAT24C00 will continue to transmit data. If no
acknowledge is sent by the Master, the device terminates
data transmission and waits for a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are fixed
as 1010 for the CAT24C00 (see Fig. 5). The next three
significant bits are "don't care" bits. The last bit of the
slave address specifies whether a Read or Write operation
is to be performed. When this bit is set to 1, a Read
operation is selected, and when set to 0, a Write operation
is selected.
After the Master sends a START condition and the slave
address byte, the CAT24C00 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24C00 then performs a Read or Write operation
depending on the state of the R/W bit.
Acknowledge
WRITE OPERATION
Byte Write
After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
Figure 4. Acknowledge Timing
i
D
c
s
SCL FROM
MASTER
n
o
START
i
t
1
u
n
In the Write mode, the Master device sends the START
condition and the slave address information (with the R/
W
bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends the byte
address that is to be written into the address pointer of
the CAT24C00. After receiving another acknowledge
from the Slave, the Master device transmits the data
byte to be written into the addressed memory location.
The CAT24C00 acknowledges once more and the
Master generates the STOP condition, at which time the
device begins its internal programming cycle to
nonvolatile memory. While this internal cycle is in
progress, the device will not respond to any request
from the Master device.
d
e
a
P
t
r
After a write command, the internal address counter
will continue to point to the same address location
that was just written. If a stop bit is transmitted to the
device at any point in the write sequence before the
entire sequence is complete, then the command will
abort and no data will be written. If more than eight
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
5020 FHD F06
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 1027, Rev. O
FPGA/CPLD
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