EVALUATION KIT AVAILABLE
MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
General Description
The MAX155/MAX156 are high-speed, 8-bit, multichan-
nel analog-to-digital converters (ADCs) with simultaneous
track/holds (T/Hs) to eliminate timing differences between
input channel samples. The MAX155 has 8 analog input
channels and the MAX156 has 4 analog input channels.
Each channel has its own T/H, and all T/Hs sample at the
same instant. The ADC converts a channel in 3.6µs and
stores the result in an internal 8x8 RAM. The MAX155/
MAX156 also feature a 2.5V internal reference and
power-down capability, providing a complete, sampling
data-acquisition system.
When operating from a single +5V supply, the MAX155/
MAX156 perform either unipolar or bipolar, single-ended
or differential conversions. For applications requiring
wider dynamic range or bipolar conversions around
ground, the V
SS
supply pin may be connected to -5V.
Conversions are initiated with a pulse to the
WR
pin, and data
is accessed from the ADC’s RAM with a pulse to the
RD
pin.
A bidirectional interface updates the channel configuration
and provides output data. The ADC may also be wired for
output-only operation.The MAX155 comes in 28-pin PDIP
and wide SO packages, and the MAX156 comes in 24-pin
narrow PDIP and 28-pin wide SO packages.
Features
●
8 Simultaneously Sampling Track/Hold Inputs
●
3.6µs Conversion Time Per Channel
●
Unipolar or Bipolar Input Range
●
Single-Ended or Differential Inputs
●
Mixed Input Configurations Possible
●
2.5V Internal Reference
●
Single +5V or Dual ±5V Supply Operation
Applications
●
●
●
●
●
Phase-Sensitive Data Acquisition
Vibration and Waveform Analysis
DSP Analog Input
AC Power Meters
Portable Data Loggers
Ordering Information
appears at end of data sheet.
For related parts and recommended products to use with this part, refer
to
www.maximintegrated.com/MAX155.related.
Functional Diagram
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
T/H
T/H
T/H
T/H
T/H
T/H
T/H
T/H
8
CONTROL
LOGIC
8x8
RAM
8-BIT
A/D
3.6µs
8
8
MAX155
CLK
REFIN
2.5V
V
REF
THREE-
STATE
BUFFER
8
REFOUT
8-BIT
DATA
8 BUS
CS
RD
WR
MODE
19-2949; Rev 2; 1/12
MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
Absolute Maximum Ratings
V
DD
to AGND ............................................................. -0.3V, +6V
V
DD
to DGND ............................................................. -0.3V, +6V
AGND to DGND ...........................................-0.3V, (V
DD
+ 0.3V)
V
SS
to AGND.............................................................. +0.3V, -6V
V
SS
to DGND ............................................................. +0.3V, -6V
CS, WR, RD,
CLK, MODE to DGND ...........-0.3V, (V
DD
+ 0 3V)
BUSY, D0–D7 to DGND ...............................-0.3V, (V
DD
+ 0 3V)
REFOUT to AGND .......................................-0.3V, (V
DD
+ 0 3V)
REFIN to AGND ...........................................-0.3V, (V
DD
+ 0 3V)
AIN to AGND .................................... (V
SS
- 0.3V), (V
DD
+ 0 3V)
Output Current (REFOUT) .................................................30mA
Continuous Power Dissipation (T
A
= +70°C)
24-Pin PDIP (derate 8.7mW/°C above +70°C) ............696mW
28-Pin PDIP (derate 9.09mW/°C above +70°C) ..........727mW
28-Pin Wide SO (derate 12.5mW/°C above +70°C) ..1000mW
Operating Temperature Ranges:
MAX155/MAX156_C_ _ ......................................0°C to +70°C
MAX155/MAX156_E_ _ .................................. -40°C to +85°C
Storage Temperature Range ............................ -65°C to +150°C
Lead Temperature (soldering, 10s) ................................. +300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(V
DD
= +5V, V
REFIN
= +2.5V. External Reference, V
AGND
= V
DGND
= 0V, V
SS
= 0V or -5V, f
CLK
= 5MHz external, Unipolar range
single-ended mode, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
ACCURACY (Note 1)
Resolution
Integral Linearity Error
No Missing Codes Resolution
Offset Error (Unipolar)
Offset Error (Bipolar)
MAX15_A
MAX15_B
Guaranteed monotonic
MAX15_A
MAX15_B
MAX15_A
MAX15_B
Unipolar
Gain Error
Bipolar
Channel-to-Channel Matching
MAX15_A
MAX15_B
MAX15_A
MAX15_B
MAX15_A
MAX15_B
MAX15_A
MAX15_B
±½
±1
48
47
-60
-62
4
20
4
8
±½
±1
±1
±2
±1
±1
±1
±2
LSB
LSB
8
±½
±1
Bits
LSB
Bits
LSB
LSB
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE (V
IN
= 50kHz, 2.5V
P-P
sine wave sampled at 220ksps)
Signal-to-Noise and Distortion
Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
Small-Signal Bandwidth
Aperture Delay
Aperture Delay Matching (Note 2)
SINAD
THD
SFDR
dB
dB
dB
MHz
ns
ns
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Maxim Integrated
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2
MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
Electrical Characteristics (continued)
(V
DD
= +5V, V
REFIN
= +2.5V. External Reference, V
AGND
= V
DGND
= 0V, V
SS
= 0V or -5V, f
CLK
= 5MHz external, Unipolar range
single-ended mode, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
ANALOG INPUT
Voltage Range, Unipolar, Single-
Ended
Unipolar Differential
Bipolar, Single-Ended
Bipolar, Differential
Common-Mode Range
DC Input Impedance
REFERENCE INPUT
REFIN Range (For Specified
Performance) (Note 2)
I
REF
REFERENCE OUTPUT (C
L
= 4.7µF)
T
A
= +25°C
Output Voltage
Load Regulation
Power-Supply Sensitivity
Temperature Drift
LOGIC INPUTS (Mode = Open Circuit)
CS, RD, WR,
CLK, D0–D7 (When
Inputs) Input Low Voltage
Input High Voltage
Input Current
Input Capacitance (Note 2)
MODE
Input Low Voltage
Input High Voltage
Input Midlevel Voltage
Input Floating Voltage
Input Current
V
IL
V
IH
V
MID
V
FLT
I
IN
V
DD
-
0.5
V
DD
/2
- 0.5
V
DD
/2
±50
±100
V
DD
/2
+ 0.5
0.5
V
V
V
V
µA
V
IL
V
IH
I
IN
C
IN
2.4
±10
15
0.8
V
V
µA
pF
I
L
= 0mA
T
A
= T
MIN
to
T
MAX
2.44
2.38
2.50
2.50
2.56
2.62
-10
±1
±100
±3
V
mV
mV
ppm/°C
V
REFIN
= 2.5V
2.375
2.500
2.625
1
V
mA
AIN_(+) to AGND
AIN_(+) to AIN_(-)
AIN_(+) to AGND
AIN_(+) to AIN_(-)
Differential mode
AIN = V
DD
0
0
-V
REF
-V
REF
V
SS
10
V
REF
V
REF
V
REF
V
REF
V
DD
MΩ
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
T
A
= +25°C, I
OUT
= 0 to 10mA
T
A
= +25°C, V
DD
= 5V ±5%
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Maxim Integrated
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3
MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
Electrical Characteristics (continued)
(V
DD
= +5V, V
REFIN
= +2.5V. External Reference, V
AGND
= V
DGND
= 0V, V
SS
= 0V or -5V, f
CLK
= 5MHz external, Unipolar range
single-ended mode, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
LOGIC OUTPUTS
BUSY, D0–D7 Output Low Voltage
Output High Voltage
D0–D7 Floating State Leakage
Floating State Output Capacitance
(Note 2)
Conversion Time
POWER REQUIREMENTS
Positive Power-Supply Voltage
V
DD
PD = 0
Positive Power-Supply Current
I
DD
PD = 1
MAX155
MAX156
CLK,
CS, WR,
RD = 0V or V
DD
;
D
OUT
= 0V or
V
DD
0
PD = 0
PD = 1
V
DD
= 5V ±5%, V
SS
= 0V
V
DD
= 5V, V
SS
= -5V ±5%
2
2
±0.1
±0.1
4.75
18
9
5.25
24
12
V
mA
C
OUT
f
CLK
= 5MHz, single channel
3.6
V
OL
V
OH
I
OUT
= 1.6mA
I
OUT
= -360µA
4
±10
15
3.8
0.4
V
V
µA
pF
µs
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
25
100
µA
Negative Power-Supply Voltage
Negative Power-Supply Current
Power-Supply Rejection (Change
in Full-Scale Error)
V
SS
I
SS
-5
50
50
±0.25
V
µA
LSB
TIMING CHARACTERISTICS (Note 3, Figures 1–7)
(V
DD
= +5V, V
REFIN
= +2.5V. External Reference, V
AGND
= V
DGND
= 0V, V
SS
= 0V or -5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
CS
to
WR
Setup Time
CS
to
WR
Hold Time
CS
to
RD
Setup Time
CS
to
RD
Hold Time (Note 2)
WR
Low Pulse Width
RD
Low Pulse Width
RD
High Pulse Width (Note 2)
WR
to
RD
Delay (Note 2)
WR
to
BUSY
Low Delay
SYMBOL
t
CWS
t
CWH
t
CRS
t
CRH
t
WR
t
RDL
t
RDH
t
WRD
t
WBD
MAX15_C/E
MAX15_C/E
MAX15_C/E
MAX15_C/E
MAX15_C/E
CONDITIONS
MIN
0
0
0
0
100
100
180
280
220
2000
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
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4
MAX155/MAX156
8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
TIMING CHARACTERISTICS (Note 3, Figures 1-7) (continued)
(V
DD
= +5V, V
REFIN
= +2.5V. External Reference, V
AGND
= V
DGND
= 0V, V
SS
= 0V or -5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
BUSY
High to
WR
Delay (to update
configuration register) (Notes 2, 3)
CLK to
WR
Delay (Acquisition Time)
(Note 2)
BUSY
High to
RD
Delay (Notes 2, 3)
Address-Setup Time
Address-Hold Time
RD
to Data Valid (Note 4)
RD
to Data Three-State Output (Note 5)
CLK to
BUSY
Delay (Note 2)
CLK Frequency
SYMBOL
t
BWD
t
ACQ
t
BRD
t
AS
t
AH
t
DV
t
TR
t
CB
0.5
MAX15_C/E
MAX15_C/E
CONDITIONS
MIN
50
800
50
120
0
100
80
100
300
5.0
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
MHz
Note 1:
V
DD
= +5V, V
REFIN
= +2.5V, V
SS
= 0V. Performance at ±5% power-supply tolerance is guaranteed by Power-Supply
Rejection test.
Note 2:
Guaranteed by design, not production tested.
Note 3:
All input control signals are specified with t
r
= t
f
= 20ns (10% to 90% of +5V) and timed from a +1.6V voltage level. Output
signals are timed from V
OH
and V
OL
.
Note 4:
t
DV
is the time required for an output to cross +0.8V or +2.4V measured with load circuit of Figure 1.
Note 5:
t
TR
is the time required for the data lines to change 0.5V, measured with load circuits of Figure 2.
+5V
3kΩ
DN
100pF
3kΩ
DN
100pF
DGND
HIGH-Z TO V
OL
DGND
HIGH-Z TO V
OH
V
OH
TO HIGH-Z
+5V
3kΩ
DN
10pF
3kΩ
V
OL
TO HIGH-Z
DN
10pF
Figure 1. Load Circuits for Data-Access Timing
Figure 2. Load Circuits for Three-State Output Timing
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