BU-65178/65179*/61588/61688*/61689*
MINIATURE ADVANCED
COMMUNICATION ENGINE
(MINI-ACE) AND MINI-ACE PLUS*
Make sure the next
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has...
®
FEATURES
•
5 Volt Only
•
Fully Integrated MIL-STD-1553 A/B
STANAG 3838 Compliant Terminals
•
One-Square-Inch Package
•
Smallest BC/RT/MT In The Industry
•
Hardware and Software
Compatible with BU-61580 ACE
Series
•
Flexible Processor/Memory
Interface
•
Bootable RT* Option
•
4K x 16 or 64K x 16* Shared RAM
DESCRIPTION
The BU-61588 Mini-ACE and BU-61688 Mini-ACE Plus* integrates two
5-volt-only transceivers, protocol, memory management, processor interface
logic, and 4K x 16, or 64K x 16* words of RAM in a choice of pin grid array
(PGA), quad flat pack or gull lead packages. The Mini-ACE is packaged in a
1.0 square inch, low profile, cofired ceramic multi-chip-module (MCM) pack-
age making it the smallest integrated MIL-STD-1553 BC/RT/MT in the indus-
try.
The Mini-ACE provides full compatibility to DDC’s BU-61580 and BU-65170
Advanced Communication Engine (ACE). As such, the Mini-ACE includes all
the hardware and software architectural features of the ACE.
The Mini-ACE contains internal address latches and bidirectional data buffers
to provide a direct interface to a host processor bus. The memory manage-
ment scheme for RT mode provides three data structures for buffering data.
These structures, combined with the Mini-ACE’s extensive interrupt capabili-
ty, serve to ensure data consistency while off-loading the host processor.
The Mini-ACE Plus* can optionally boot-up as a RT with the Busy bit set for
1760 applications. The Mini-ACE BC mode implements several features
aimed at providing an efficient real-time software interface to the host proces-
sor including automatic retries, programmable intermessage gap times, auto-
matic frame repetition, and flexible interrupt generation.
The advanced architectural features of the Mini-ACE, combined with its small size
and high reliability, make it an ideal choice for demanding military and industrial
processor-to-1553 applications.
•
Automatic BC Retries
•
Programmable BC Gap Times
•
Programmable Illegalization
•
Simultaneous RT/Monitor Mode
•
Operates From 10*/12 /16 / 20* MHz
Clock
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
All trademarks are the property of their respective owners.
©
1998, 1999 Data Device Corporation
Data Device Corporation
www.ddc-web.com
4K X 16
OR
64K X 16
SHARED
RAM
TX/RX_A
*
CH. A
TRANSCEIVER
A
TX/RX_A
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
ADDRESS BUS
ADDRESS
BUFFERS
DATA BUS
DATA
BUFFERS
D15-D0
PROCESSOR
DATA BUS
TX/RX_B
A15-A0
PROCESSOR
ADDRESS BUS
2
TRANSCEIVER
B
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
IOEN, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
INT
PROCESSOR
AND
MEMORY
CONTROL
INTERRUPT
REQUEST
RTAD4-RTAD0, RTADP
CLK_IN,
MSTCLR,SSFLAG/EXT_TRG
CH. B
TX/RX_B
RT ADDRESS
RT_AD_LAT
MISCELLANEOUS
BU-65178/65179*/61688*/61689*
M-11/06-0
FIGURE 1. BU-65178/65179*/61588/61688*/61689*
TABLE 1. BU-65178/65179*/61588/61688*/61689*
SPECIFICATIONS
PARAMETER
ABSOLUTE MAXIMUM RATING
Supply Voltage
Logic +5 V
Transceiver +5 V (Note 12)
Logic
Voltage Input Range
RECEIVER
Differential Input Resistance
(Notes 1-7)
Differential Input Capacitance
(Notes 1-7)
Threshold Voltage, Transformer
Coupled, Measured on Stub
Common Mode Voltage (Note 7)
TRANSMITTER
Differential Output Voltage
Direct Coupled Across 35
Ω,
Measured on Bus
Transformer Coupled Across
70
Ω,
Measured on Bus:
• Standard Product = – XX0
• 1760 Amplitude Compliant
Product = – XX2
( Note 13 and Ordering
Information – Test Criteria)
Output Noise, Differential (Direct
Coupled)
Output Offset Voltage, Transformer
Coupled Across 70 ohms
Rise/Fall Time
LOGIC
VIH
VIL
IIH (Vcc = 5.5 V, VIN = Vcc)
IIH (Vcc = 5.5 V, VIN = 2.7 V)
SSFLAG/EXT_TRIG
All Other Inputs
IIL (Vcc = 5.5 V, VIN = 0.4 V)
SSFLAG/EXT_TRIG
All Other Inputs
VOH (Vcc = 4.5 V, VIH = 2.7 V,
VIL = 0.2 V, IOH = max)
VOL (Vcc = 4.5 V, VIH = 2.7 V,
VIL = 0.2 V, IOL = max)
IOL
DB15-DB0
A15-A0
MEMOE/ADDR_LAT
MEMWR/ZEROWAIT
DTREQ/16/8
DTACK/POLARITY_SEL
INT
READYD
IOEN
IOH
DB15-DB0
A15-A0
MEMOE/ADDR_LAT
MEMWR/ZEROWAIT
DTREQ/16/8
DTACK/POLARITY_SEL
INT
READYD
IOEN
CI (Input Capacitance)
CIO (Bi-directional signal input
capacitance)
MIN
TYP
MAX
UNITS
TABLE 1. BU-65178/65179*/61588/61688*/61689*
SPECIFICATIONS (CONT.)
PARAMETER
1553 MESSAGE TIMING
Completion of CPU Write (BC
Start)- to-Start of Next Message
BC Intermessage Gap (Note 8)
BC/RT/MT Response Timeout
(Note 9)
18.5 nominal
22.5 nominal
50.5 nominal
128.0 nominal
T Response Time (Note 11)
Transmitter Watchdog Timeout
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
BU-65178/61588X3
• +5 V (Logic)
• +5 V (Ch. A, Ch. B)
Current Drain (Total Hybrid)
BU-65178/65179/61588X0
• +5 V (Logic)
BU-65178/65179/61588X3
• +5 V (Logic, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
BU-61688*/61689X0*
• +5 V (Logic)
BU-61688*/61689X3*
• +5 V (Logic, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
POWER DISSIPATION
Total Hybrid
BU-65178/65179/61588X0
• +5 V (Logic)
BU-65178/61588/65179X3
• Idle
• 25% Duty Cycle
• 50% Duty Cycle
• 100% Duty Cycle
BU-61688*/61689X0*
• +5 V (Logic)
BU-61688*/61689X3*
• Idle
• 25% Duty Cycle
• 50% Duty Cycle
• 100% Duty Cycle
Hottest Die
BU-65178/61588X3/65179X3*/
BU-61688*/61689X3*
• Idle
• 25% Duty Cycle
• 50% Duty Cycle
• 100% Duty Cycle
MIN
TYP
MAX
UNITS
-0.3
-0.3
-0.3
2.5
6.0
7.0
Vcc+0.3
V
V
V
kohm
2.5
9.5
μs
μs
μs
μs
μs
μs
μs
μs
5
0.20
0
0.860
10
pF
Vp-p
Vpeak
17.5 18.5
21.5 22.5
49.5 50.5
127 129.5
4
668
19.5
23.5
51.5
131
7
6
7
9
Vp-p
4.5
4.75
5.0
5.0
5.5
5.25
V
V
23
100
mA
18
20
21
22
27
27
Vp-p
Vp-p
10
-250
100
2.0
-10
-692
-346
-794
-397
2.4
0.8
10
-84
-42
-100
-50
150
250
300
mVp-p,
diff
mV
nsec
V
V
μA
μA
μA
μA
μA
V
V
116
222
328
540
46
160
265
370
580
200
mA
mA
mA
mA
mA
116
217
318
519
180
285
390
600
mA
mA
mA
mA
0.115
0.64
0.93
1.22
1.81
0.230
0.64
0.93
1.22
1.80
0.5
0.88
1.11
1.33
1.97
1.0
0.99
1.22
1.45
1.90
W
W
W
W
W
W
W
W
W
W
0.4
6.4
mA
3.2
mA
-6.4
mA
0.18
0.42
0.66
1.14
0.28
0.51
0.75
1.22
W
W
W
W
-3.2
mA
*
Mini-ACE PLUS with 64K Words of RAM. RAM impact to Power
Supply is based on Host Processor activity; subtract 140 mA if Host
is idle.
50
50
pF
pF
Data Device Corporation
www.ddc-web.com
3
BU-65178/65179*/61688*/61689*
M-11/06-0
TABLE 1. BU-65178/65179*/61588/61688*/61689*
SPECIFICATIONS (CONT.)
PARAMETER
Frequency
BU-61588/61688*/65178
• Default Mode
• Software Programmable Option
BU-61689*
• Default Mode
• Software Programmable Option
BU-65179*
• Pin Programmable Option
Long Term Tolerance
• 1553A Mode
• 1553B Mode
Short Term Tolerance, 1 second
• 1553A Mode
• 1553B Mode
Duty Cycle
• 16 MHz
• 12 MHz
• 10 MHz*
• 20 MHz
THERMAL
Thermal Resistance, Junction-to-
Case, Hottest Die (θJC)
BU-65178/61588X3*
Operating Junction Temperature
Storage Temperature
Lead Temperature (soldering, 10
sec.)
PHYSICAL CHARACTERISTICS
Size
BU-65178/61588 P
BU-65179*/61688*/61689*
BU-65178/61588 F/G
BU-65179*/61688*/61689*
Weight
BU-65178/61588 F/P/G
BU-65179*/61688*/61689*
MIN
TYP
MAX
UNITS
Table 1 Notes (Cont.):
(8) Typical value for minimum intermessage gap time. Under software
control, may be lengthened to (65,535
μs
minus message time), in
increments of 1
μs.
(9) Software programmable (4 options). Includes RT-to-RT Timeout (Mid-
Parity of Transmit Command to Mid-Sync of Transmitting RT Status).
(10) For both +5 V logic and transceiver. +5 V for channels A and B.
(11) Measured from mid-parity crossing of Command Word to mid-sync
crossing of RT’s Status Word.
(12) External 10
μF
Tantalum and 0.1
μF
capacitors should be located
as close as possible to Pins 20 and 72 on the Flat Package
and Pins A9 and J3 on the PGA package, and 0.1
μF
at Pin 37/D3.
(13) MIL-STD–1760 requires that the Mini-ACE produce a 20 Vp-p min-
imum output on the stub connection.
16
12
20
10
10/12/16/20
MHz
MHz
MHz
MHz
MHz
0.01
0.1
0.001
0.01
33
40
40
40
67
60
60
60
%
%
%
%
%
%
%
%
-55
-65
6.8
150
150
+300
°C/W
°C
°C
°C
1.0 X 1.0 X 0.150
(25.4 x 25.4 x 3.81)
1.0 X 1.0 X 0.155
(25.4 x 25.4 x 3.94)
in.
(mm)
in.
(mm)
0.3
(9)
oz
(g)
Notes: Notes 1 through 6 are applicable to the Receiver Differential
Resistance and Differential Capacitance specifications:
(1) Specifications include both transmitter and receiver (tied together internally).
(2) Measurement of impedance is directly between pins TX/RX A(B)
and TX/RX A(B) of the BU-65178/61588X3 hybrid.
(3) Assuming the connection of all power and ground inputs to the hybrid.
(4) The specifications are applicable for both unpowered and powered conditions.
(5) The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
(6) Minimum resistance and maximum capacitance parameters are
guaranteed, but not tested, over the operating range.
(7) Assumes a common mode voltage within the frequency range of dc to 2
MHz, applied to pins of the isolation transformer on the stub side (either direct
or transformer coupled), referenced to hybrid ground. Use a DDC recom-
mended transformer or other transformer that provides an equivalent CMRR.
Data Device Corporation
www.ddc-web.com
4
BU-65178/65179*/61688*/61689*
M-11/06-0
TABLE 2. BU-65178/65179*/61588/61688*/61689* PIN
LISTINGS (QFP QUAD FLAT PACK, PGA-PIN GRID
ARRAY AND GULL LEAD)
QFP PGA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
B4
B5
C2
C3
C1
D2
D1
C4
E3
F2
E1
F3
G1
G4
G3
H1
A7
A8
J8
A9
J7
F1
J2
H5
H3
H4
G2
J5
J6
H6
G7
H2
H7
G8
H8
E8
D3
F8
G6
G9
J9
NAME
MEM/REG
MSTCLR
A11
A10
TX/RX-A
A08
TX/RX-A
A14, See NOTE 1
A04
A03
A07
A02
TX/RX-B
MEMOE/ADDR_LAT
A00
TX/RX-B
LOGIC GND
LOGIC GND
LOGIC GND
+5V V
CC2
RTAD2
A06
MEMWR/
ZEROWAIT
DTREQ/16/8
Test Output (RX-B)
Test Output (RX-B)
A01
MEMENA_IN/
TRIGGER_SEL
DTACK/
POLARITY_SEL
CLOCK_IN
RT_AD_LAT
SSFLAG/EXT_TRIG
RTAD0
RTAD3
RTAD4
D06
+5V V
CC
D01
D04
RTADP
RTAD1
**
**
**
N/A
F4
F5
F6
E5
**
**
**
**
QFP
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
**
PGA
H9
F9
F7
G5
E7
E9
D7
B2
D9
B9
A2
D8
A1
C9
B8
C8
A3
B7
C7
C6
A6
A5
J1
A4
C5
B6
E2
J4
B3
B1
J3
D4
D5
D6
E4
E6
D00
D02
D03
D05
D08
D07
D13
D12
D14
D09
D11
D15
D10
TRANSPARENT/
BUFFERED
READYD
INT
IOEN
TX_INH_A
TX_INH_B
SELECT
STRBD
RD/WR
DTGRT/MSB/LSB
Test Output (RX-A)
A15, See NOTE 1
Test Output (RX-A)
A05
A09
A12, See NOTE 2
A13, See NOTE 3
+5V V
CC1
TestOutput(A_RExt)
Test Output
(A_Test1)
Test Output
(AB_Test4)
TestOutput(B_RExt)
TestOutput
(AB_Tstck)
TestOutput
(AB_Test2)
TestOutput
(AB_Test3)
TestOutput
(B_Test1)
No Connect
NAME
NOTES
** Note that the Test Output pins on the flat pack are pads located on
the bottom of the package.
1. BU-65179*, A15/A14 pins are actually CLK SEL 1 / CLK SEL 0 respectively.
2. BU-65179*, A12 pin selects the RT_BOOT_L OPTIONAL MODE.
3. BU-65179*, A13 pin has no connection.
Data Device Corporation
www.ddc-web.com
5
BU-65178/65179*/61688*/61689*
M-11/06-0
实时操作系统RTOS
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