DATA SHEET
CX72301: Spur-Free, 1.0 GHz Dual Fractional-N Frequency
Synthesizer
Applications
•
General purpose RF systems
•
Low bit rate wireless telemetry
•
Instrumentation
•
Specialized Mobile Radios (SMRs) and Private Mobile Radios
(PMRs)
synthesizer is a key building block for high-performance radio
system designs that require low power and fine step size.
The ultra-fine step size of less than 100 Hz allows this synthesizer
to be used in very narrowband wireless applications. With proper
temperature sensing or through control channels, the
synthesizer’s fine step size can compensate for crystal oscillator
or Intermediate Frequency (IF) filter drift. As a result, crystal
oscillators or crystals can replace temperature- compensated or
ovenized crystal oscillators, reducing parts count and associated
component cost. The device’s fine step size can also be used for
Doppler shift corrections.
The CX72301 has a phase noise floor of –95 dBc/Hz up to
1.0 GHz operation as measured inside the loop bandwidth. This is
permitted by the on-chip low noise dividers and low divide ratios
provided by the device’s high fractionality.
Reference crystals or oscillators up to 50 MHz can be used with
the CX72301. The crystal frequency is divided down by
independent programmable divider ratios of 1 to 32 for the main
and auxiliary synthesizers. The phase detectors can operate at a
maximum speed of 25 MHz, which allows better phase noise due
to the lower division value. With a high reference frequency, the
loop bandwidths can also be increased. Larger loop bandwidths
improve the settling times and reduce in-band phase noise.
Therefore, typical switching times of less than 100
µs
can be
achieved. The lower in-band phase noise also permits the use of
lower cost Voltage Controlled Oscillators (VCOs) in customer
applications.
The CX72301 has a frequency power steering circuit that helps
the loop filter steer the VCO when the frequency is too fast or too
slow, further enhancing acquisition time.
The unit operates with a three-wire, high-speed serial interface. A
combination of a large bandwidth, fine resolution, and the three-
wire, high-speed serial interface allows for a direct frequency
modulation of the VCO. This supports any continuous phase,
constant envelope modulation scheme such as Frequency
Modulation (FM), Frequency Shift Keying (FSK), Minimum Shift
Keying (MSK), or Gaussian Minimum Shift Keying (GMSK). This
capability can eliminate the need for In-Phase and Quadrature
(I/Q) Digital-To-Analog Converters (DACs), quadrature
upconverters, and IF filters from the transmitter portion of the
radio system.
Figure 1 shows a functional block diagram for the CX72301. The
device package and pinout for the 28-pin Exposed Pad Thin
Shrink Small Outline Package (EP-TSSOP) are shown in Figure 2.
Features
•
Spur-free operation
•
1.0 GHz maximum operating frequency
•
500 MHz maximum auxiliary synthesizer
•
Ultra-small step size, 100 Hz or less
•
High internal reference frequency enables large loop bandwidth
implementations
•
Very fast switching speed (e.g., below 100
µs)
•
Phase noise to –96 dBc/Hz inside the loop filter bandwidth
@ 950 MHz
•
Software programmable power-down modes
•
High-speed serial interface up to 100 Mbps
•
Three-wire programming
•
Programmable division ratios on reference frequency
•
Phase detectors with programmable gain provide a
programmable loop bandwidth
•
Frequency power steering further enhances rapid acquistion
time
•
On-chip crystal oscillator
•
Frequency adjust for temperature compensation
•
Direct digital modulation
•
3 V operation
•
5 V output to loop filter
•
28-pin EP-TSSOP 6.4 x 9.7 mm package
Description
Skyworks CX72301 direct digital modulation fractional-N
frequency synthesizer provides ultra-fine frequency resolution,
fast switching speed, and low phase-noise performance. This
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
101090H • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 21, 2004
1
DATA SHEET • CX72301
Data
Clock
CS
Serial
Interface
Modulator
Data
Main
∆Σ
Main
Divider
Registers
Modulator
Control
Ref.
Divider
Synth
Control
Aux.
Divider
Aux.
∆Σ
Mod_in
Modulation
Unit
Mux
Mux_out
∆Σ
18-Bit
∆Σ
10-Bit
Fractional
Unit
Fvco_main
Fvco_main
Main
Divider
Main
Divider
Fpd_main
Reference
Frequency
Oscillator
Fractional
Unit
Fvco_aux
Auxiliary
Divider
Auxiliary
Prescaler
Fvco_aux
Fref_main
Fref_aux
Fpd_aux
Main
Phase/Freq.
Detector
and
Charge Pump
Fref
Reference
Frequency
Oscillator
Auxiliary
Phase/Freq.
Detector
and
Charge Pump
CPout_main
Lock Detection or
Power Steering
LD/PSmain
CPout_aux
LD/PSaux
Lock Detection or
Power Steering
C1447
Figure 1. CX72301 Functional Block Diagram
Clock
Mod_in
Mux_out
VSUBdigital
GNDcml
VCCcml_main
Fvco_main
Fvco_main
LD/PSmain
VCCcp_main
CPout_main
GNDcp_main
Xtalacgnd/OSC
Xtalin/OSC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CS
Data
VCCdigital
GNDdigital
VCCcml_aux
Fvco_aux
Fvco_aux
GNDcp_aux
CPout_aux
VCCcp_aux
LD/PSaux
GNDxtal
VCCxtal
Xtalout/NC
C1412
Figure 2. CX72301 Pinout, 28-Pin EP-TSSOP
(Top View)
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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July 21, 2004 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 101090H
DATA SHEET • CX72301
Technical Description
The CX72301 is a fractional-N frequency synthesizer using a
∆Σ
modulation technique. The fractional-N implementation provides
low in-band noise by having a low division ratio and fast
frequency settling time. In addition, the CX72301 provides
arbitrarily fine frequency resolution with a digital word, so that the
frequency synthesizer can be used to compensate for crystal
frequency drift in the RF transceiver.
Serial Interface
The serial interface is a versatile three-wire interface consisting of
three pins: Clock (serial clock), Data (serial input), and CS (chip
select). It enables the CX72301 to operate in a system where one
or multiple masters and slaves are present. To perform a
loopback test at start-up and to check the integrity of the board
and processor, the serial data is fed back to the master device
(e.g., a microcontroller or microprocessor unit) through a
programmable multiplexer. This facilitates hardware and software
debugging.
Registers
There are ten 16-bit registers in the CX72301. For more
information, see the Register Descriptions section of this
document.
Main and Auxiliary
∆Σ
Modulators
The fractionality of the CX72301 is accomplished by the use of a
proprietary, configurable 10-bit or 18-bit
∆Σ
modulator for the
main synthesizer and 10-bit
∆Σ
modulator for the auxiliary
synthesizer.
Main and Auxiliary Fractional Units
The CX72301 provides fractionality through the use of main and
auxiliary
∆Σ
modulators. The output from the modulators is
combined with the main and auxiliary divider ratios through their
respective fractional units.
VCO Prescalers
The VCO prescalers provide low-noise signal conditioning of the
VCO signals. They translate from an off-chip, single-ended or
differential signal to an on-chip differential Current Mode Logic
(CML) signal. The CX72301 has independent main and auxiliary
VCO prescalers.
Main and Auxiliary VCO Dividers
The CX72301 provides programmable dividers that control the
CML prescalers and supply the required signals to the charge
pump phase detectors. Programmable divide ratios ranging from
38 to 537 are possible in fractional-N mode and from 32 to 543 in
integer-N mode.
Reference Frequency Oscillator
The CX72301 has a self-contained, low-noise crystal oscillator.
This crystal oscillator is followed by the clock generation circuitry
that generates the required clock for the programmable reference
frequency dividers.
Reference Frequency Dividers
The crystal oscillator signal can be divided by a ratio of 1 to 32 to
create the reference frequencies for the phase detectors. The
CX72301 has both a main and an auxiliary frequency synthesizer,
and provides independently configurable dividers of the crystal
oscillator frequency for both the main and auxiliary phase
detectors. The divide ratios are programmed through the
Reference Frequency Dividers Register.
NOTE:
The divided crystal oscillator frequencies (which are the
internal reference frequencies), Fref_main and Fref_aux,
are referred to as the reference frequencies throughout
this document.
Phase Detectors and Charge Pumps
The CX72301 uses a separate charge pump phase detector for
each synthesizer which provides a programmable gain,
Kd,
from
31.25 to 1000
µA/2π
radians in 32 steps programmed using the
Control Register.
Frequency Steering
When programmed for frequency power steering, the CX72301
has a circuit that helps the loop filter steer the VCO using the
LD/PSmain signal (pin 9). In this configuration, the LD/PSmain
signal can provide a more rapid acquisition.
When programmed for lock detection, internal frequency steering
is implemented and provides frequency acquisition times
comparable to conventional phase/frequency detectors.
Lock Detection
When programmed for lock detection, the CX72301 provides an
active low, pulsing open collector output using the LD/PSmain
signal (pin 9) to indicate the out-of-lock condition. When locked,
the LD/PSmain signal is three-stated (high impedance).
Power Down
The CX72301 supports a number of power-down modes through
the serial interface. For more information, see the Register
Descriptions section of this document.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
101090H • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 21, 2004
3
DATA SHEET • CX72301
Operation
This section describes the operation of the CX72301. The serial
interface is described first, followed by information on how to
obtain values for the Divide Ratio Registers.
Serial Interface
The serial interface consists of three signals: Clock (pin 1), Data
(pin 27) and CS (pin 28). The Clock signal controls data on the two
serial data lines (Data and CS). The Data pin bits shift into a
temporary register on the rising edge of Clock. The CS line allows
individual selection transfers that synchronize and sample the
information of slave devices on the same bus.
Figure 3 functionally depicts how a serial transfer takes place.
A serial transfer is initiated when a microcontroller or
microprocessor forces the CS line to a low state. This is followed
immediately by an address/data stream sent to the Data pin that
coincides with the rising edges of the clock presented on the
Clock line.
Each rising edge of the Clock signal shifts in one bit of data on the
Data line into a shift register. At the same time, one bit of data is
shifted out of the Mux_out pin (if the serial bit stream is selected)
at each falling edge of Clock. To load any of the synthesizer
registers, 16 bits of address or data must be presented to the
Data line with the data LSB last while CS is low. If CS is low for
more than 16 clock cycles, only the last address or data bits are
used to load the synthesizer registers.
If the CS line is brought to a high state before the 13
th
clock edge
on Clock, the bit stream is assumed to be modulation data
samples. In this case, it is assumed that no address bits are
present and that all the bits in the stream should be loaded into
the Modulation Data Register.
Synthesizer Register Programming
Synthesizer register programming equations, described in this
section, use the following variables and constants:
N
fractional
Desired VCO division ratio in fractional-N applications.
This is a real number and can be interpreted as the
reference frequency (F
ref
) multiplying factor such that
the resulting frequency is equal to the desired VCO
frequency.
Desired VCO division ratio in integer-N applications.
This number is an integer and can be interpreted as
the reference frequency (F
ref
) multiplying factor so that
the resulting frequency is equal to the desired VCO
frequency.
9-bit unsigned input value to the divider ranging from
0 to 511 (integer-N mode) and from 6 to 505
(fractional-N mode).
This constant equals 262144 when the
∆Σ
modulator
is in 18-bit mode, and 1024 when the
∆Σ
modulator is
in 10-bit mode.
N
integer
N
reg
divider
dividend
When in 18-bit mode, this is the 18-bit signed input
value to the
∆Σ
modulator, ranging from
–131072 to +131071 and providing 262144 steps,
each of
F
div_ref
/2
18
Hz.
When in 10-bit mode, this is the 10-bit signed input
value to the
∆Σ
modulator, ranging from
–512 to +511 and providing 1024 steps, each of
Fdiv_ref/2
10
Hz.
F
VCO
F
div_ref
Desired VCO frequency (either F
vco_main
or F
vco_aux
).
Divided reference frequency presented to the phase
detector (either F
ref_main
or F
ref_aux
).
Clock
Data
X
A3
A2
A1
A0 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
XXX
CS
Last
C1413
Figure 3. Serial Transfer Timing Diagram
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July 21, 2004 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 101090H
DATA SHEET • CX72301
Fractional-N Applications.
The desired division ratio for the
main and auxiliary synthesizer is given by the following equation:
F
VCO
N
f rac tion al
= ------------------
-
F
di v_r ef
The value to be programmed in the Main or Auxiliary Dividend
Register is given by the following equation:
dividend
=
R ound divider
N
f ra ctio nal
–
N
reg
–
32
where
N
fractional
must be between 37.5 and 537.5.
The value to be programmed in the Main or Auxiliary Divider
Register is given by the equation:
N
r eg
=
R ound N
fr actio nal
–
32
where the divider is either 1024 in 10-bit mode or 262144 in
18-bit mode. Therefore, the dividend is a signed binary value
either 10 or 18 bits long.
NOTE:
Because of the high fractionality of the CX72301, there is
no practical need for any integer relationship between
the reference frequency and the channel spacing or
desired VCO frequencies.
Sample calculations for two fractional-N applications are provided
in Figure 4.
NOTE:
The Round function rounds the number to the nearest
integer.
When in fractional mode, allowed values for
N
reg
are from 6 to
505, inclusive.
Case 1:
To achieve a desired F
vco_main
frequency of 902.4530 MHz using a crystal frequency of 40 MHz with operation
of the synthesizer in 18-bit mode. Since the maximum internal reference frequency (F
div_ref
) is 25 MHz, the crystal
frequency is divided by 2 to obtain a F
div_ref
of 20 MHz. Therefore:
Nfractional = Fvco_main
Fdiv_ref
= 902.4530
20
= 45.12265
The value to be programmed in the Main Divider Register is:
Nreg = Round[Nfractional] – 32
= Round[45.12265] – 32
= 45 – 32
= 13
(decimal)
=
000001101
(binary)
With the modulator in 18-bit mode, the value to be programmed in the Main Dividend Registers is:
dividend = Round[divider × (Nfractional – Nreg – 32)]
= Round[262144 × (45.12265 – 13 – 32)]
= Round[262144 × (0.12265)]
= Round[32151.9616]
= 32152
(decimal)
= 000111110110011000
(binary)
where 00 0111 1101 is loaded in the MSB of the Main Dividend Register and 1001 1000 is loaded in the LSB of the
Main Dividend Register.
Summary:
·
·
·
·
·
Main Divider Register = 0 0000 1101
Main Dividend LSB Register = 1001 1000
Main Dividend MSB Register = 00 0111 1101
The resulting main VCO frequency is 902.453 MHz
Step size is 76.3 Hz
Note: The frequency step size for this case is 20 MHz divided by 2
18
, giving 76.3 Hz.
C1414
Figure 4. Fractional-N Applications: Sample Calculation (1 of 2)
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
101090H • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 21, 2004
5
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