19-3385; Rev 0; 8/04
Multiple-Output Network Clock Generator
General Description
The MAX9489 clock generator provides multiple clock
outputs, ideal for network routers. The MAX9489 pro-
vides 15 buffered clock outputs, each independently
programmable to any of 10 individual frequencies:
133MHz, 125MHz, 100MHz, 83MHz, 80MHz, 66MHz,
62.5MHz, 50MHz, 33MHz, or 25MHz. All of the outputs
are single-ended LVCMOS. The MAX9489 is controlled
through its I
2
C™ interface.
At power-up, the frequency of output CLK1 is set by the
tri-level input SEL to 100MHz, 125MHz, or 133MHz,
while all other outputs are logic low. All outputs are then
programmable to any available frequency through the
I
2
C interface. Additionally, all output frequencies are
adjustable up or down, by a margin of 5% or 10%,
through the I
2
C interface.
The MAX9489 requires a 25MHz reference that can be
either a crystal or an external clock signal. The
MAX9489 requires a +3.0V to +3.6V power supply and
is available in a 32-pin thin QFN package with an
exposed pad for heat removal.
Features
♦
15 LVCMOS Outputs with 10 Independently
Programmable Frequencies: 133MHz, 125MHz,
100MHz, 83MHz, 80MHz, 66MHz, 62.5MHz, 50MHz,
33MHz, and 25MHz
♦
25MHz Crystal or Clock Input Reference
♦
Programmable Through I
2
C Interface
♦
Programmable Output Frequency Margin of ±5%
or ±10%
♦
Pin-Selectable Power-Up Frequency for CLK1
Output: 100MHz, 125MHz, or 133MHz
♦
Low Output Period Jitter: < 48ps
RMS
♦
Output-to-Output Skew < 200ps
♦
Available in 32-Lead, 5mm x 5mm x 0.8mm,
Thin QFN Package
♦
Operates from +3.0V to +3.6V Power Supply
♦
Power Dissipation 450mW (typ)
♦
Extended Temperature Range: -40°C to +85°C
MAX9489
Applications
Network Routers
Telecom/Networking Equipment
Storage Area Networks/Network Attached
Storage
Ordering Information
PART
MAX9489ETJ
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
32 Thin QFN-EP*
5mm x 5mm x 0.8mm
Pin Configuration
*EP
= Exposed pad.
CLK15
CLK14
GND
SA1
SA0
V
DD
V
DD
TOP VIEW
CLK13
Typical Operating Circuit
24 V
DD
23 CLK12
22 CLK11
21 CLK10
20 V
DD
19 CLK9
18 CLK8
32 31 30 29 28 27 26 25
GND
SCL
SDA
SEL
AV
DD
X1
X2
AGND
1
2
3
4
5
6
7
8
9
CLK1
EXPOSED PAD (GND)
10 11 12 13 14 15 16
CLK2
CLK3
CLK4
CLK5
CLK6
V
DD
V
DD
+3.3V
0.1µF
AV
DD
V
DD
+3.3V
0.1µF x 5
MAX9489
MAX9489
X1
10pF
25MHz
10pF
X2
SERIAL
INTERFACE
SDA
SCL
SA0
SA1
SEL
AGND
GND
V
DD
V
DD
V
DD
V
DD
CLK1
CLOCK
OUTPUTS
CLK15
17 CLK7
THIN QFN-EP
is a trademark of Philips Corp.
Purchase of I
2
C components of Maxim Integrated Products, Inc.,
or one of its sublicensed Associated Companies, conveys a
license under the Philips I
2
C Patent Rights to use these compo-
nents in an I
2
C system, provided that the system conforms to the
I
2
C Standard Specification as defined by Philips.
I
2
C
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Multiple-Output Network Clock Generator
MAX9489
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND ..............................................…….….-0.3V to +4.0V
AGND to GND .............................................……...-0.3V to +0.3V
All Other Pins to GND.................................-0.3V to (V
DD
+ 0.3V)
Short-Circuit Duration for all CLK_ Outputs ...............Continuous
Continuous Power Dissipation (T
A
= +70°C)
32-Pin Thin QFN (derate 21.3mW/°C above +70°C) ....1702mW
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
ESD Rating (Human Body Model) .......................................±2kV
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
DD
= AV
DD
= +3.0V to +3.6V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
DD
= AV
DD
= +3.3V, T
A
= +25°C.)
(Note 1)
PARAMETER
CLOCK INPUT (X1)
Input High Level
Input Low Level
Input Current
CLOCK OUTPUTS (CLK_)
I
OH
= -100µA
Output High Level
V
OH
I
OH
= -4mA
I
OH
= -8mA
I
OL
= 100µA
Output Low Level
Output Short-Circuit Current
Output Capacitance
TRI-LEVEL INPUTS (SEL, SA0, SA1)
Input High Level
Input Low Level
Input Open Level
Input Current
V
IH2
V
IL2
V
IO2
I
IL2
, I
IH2
V
IL2
= 0 or V
IH2
= V
DD
1.35
-10
0.7 x
V
DD
0
-1
I
SINK
= 4mA
(Note 2)
0
2.5
0.8
1.90
+10
V
V
V
µA
V
OL
I
OS
C
O
I
OL
= 4mA
I
OL
= 8mA
CLK_ = V
DD
or GND
(Note 2)
V
DD
-
0.2
2.4
2.1
0.2
0.4
0.75
45
5
mA
pF
V
V
V
IH1
V
IL1
I
IL1
, I
IH1
V
X
_ = 0 to V
DD
-5
2.0
0.8
+5
V
V
µA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SERIAL INTERFACE (SCL, SDA)
(Note 3)
Input High Level
Input Low Level
Input leakage Current
Low-Level Output
Input Capacitance
V
IH
V
IL
I
IH
, I
IL
V
OL
Ci
V
DD
0.3 x
V
DD
+1
0.4
10
V
V
µA
V
pF
2
_______________________________________________________________________________________
Multiple-Output Network Clock Generator
DC ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= AV
DD
= +3.0V to +3.6V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
DD
= AV
DD
= +3.3V, T
A
= +25°C.)
(Note 1)
PARAMETER
POWER SUPPLIES
Digital Power-Supply Voltage
Analog Power-Supply Voltage
Total Supply Current
Total Power-Down Current
I
PD
V
DD
AV
DD
C
L
= 10pf (with all CLK_ outputs at 133MHz)
All clock registers = 0x00
3.0
3.0
134
38
3.6
3.6
160
47
V
V
mA
mA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX9489
AC ELECTRICAL CHARACTERISTICS
(V
DD
= AV
DD
= +3.0V to +3.6V, C
L
= 10pF, unless otherwise noted. Typical values are at V
DD
= AV
DD
= +3.3V, T
A
= +25°C, with all
CLK_ outputs at 133MHz.) (Note 2)
PARAMETER
OUTPUTS (CLK_)
Crystal Frequency Tolerance
Output-to-Output Skew
Rise Time
Fall Time
Duty Cycle
Output Period Jitter
Power-Up Time
PLL Lockup Time
Margin Accuracy
J
P
t
PO
t
Lock
RMS
V
DD
> 2.8V to PLL lock
PLL dividing ratio set to PLL lock
Select ±5% or ±10% margin
-1
∆f
A
t
SKO
t
R1
t
F1
Any two CLK_ outputs
20% V
DD
to 80% V
DD
80% V
DD
to 20% V
DD
40
53
2
20
+1
1.8
1.8
-50
+50
200
2.5
2.5
60
ppm
ps
ns
ns
%
ps
ms
µs
%
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
_______________________________________________________________________________________
3
Multiple-Output Network Clock Generator
MAX9489
SERIAL INTERFACE TIMING
(V
DD
= AV
DD
= +3.3V, T
A
= -40°C to +85°C.) (Note 1, Figure 2)
PARAMETER
Serial Clock
Bus Free Time Between STOP
and START Conditions
Hold Time, Repeated START
Condition
Repeated START Condition
Setup Time
STOP Condition Setup Time
Data Hold Time Master
Data Hold Time Slave
Data Setup Time
SCL Clock Low Period
SCL Clock High Period
Rise Time of SDA and SCL,
Receiving
Fall Time of SDA and SCL,
Receiving
Fall Time of SDA, Transmitting
Pulse Width of Spike Suppressed
Capacitive Load for Each Bus
Line
SYMBOL
f
SCL
t
BUF
t
HD,STA
t
SU,STA
t
SU,STO
t
HD,DAT
t
HD,DAT
t
SU,DAT
t
LOW
t
HIGH
t
R
t
F
t
F,TX
t
SP
C
b
(Notes 2, 5)
(Notes 2, 5)
(Notes 2, 5)
(Notes 2, 6)
(Note 2)
(Note 4)
(Note 4)
1.3
0.6
0.6
0.6
15
15
100
1.3
0.7
20 +
0.1C
b
20 +
0.1C
b
20 +
0.1C
b
0
300
300
250
50
400
900
900
CONDITIONS
MIN
TYP
MAX
400
UNITS
kHz
µs
µs
µs
µs
ns
ns
ns
µs
µs
ns
ns
ns
ns
pF
Note 1:
All DC parameters tested at T
A
= +25°C. Specifications over temperature are guaranteed by design.
Note 2:
Guaranteed by design.
Note 3:
No high output level is specified but only the output resistance to the bus. For I
2
C, the high-level voltage is provided by
pullup resistors on the bus.
Note 4:
A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
IL
of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 5:
C
b
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3(V
DD
) and 0.7(V
DD
).
Note 6:
Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
4
_______________________________________________________________________________________
Multiple-Output Network Clock Generator
Typical Operating Characteristics
(V
DD
= 3.3V, T
A
= +25°C, unless otherwise noted.)
RISE AND FALL TIMES
vs. TEMPERATURE
MAX9489 toc02
MAX9489 toc01
MAX9489
SUPPLY CURRENT
vs. TEMPERATURE
160
150
SUPPLY CURRENT (mA)
140
130
120
110
100
-40
-15
10
35
60
85
TEMPERATURE (°C)
2.3
TRANSITION TIME (ns)
2.1
JITTER vs. TEMPERATURE
133MHz
MAX9489 toc03
70
60
RMS PERIOD JITTER (ps)
50
40
30
20
10
0
25MHz
t
FALL
1.9
t
RISE
1.7
1.4
1.2
1.0
-40
-15
10
35
60
85
TEMPERATURE (°C)
-40
-15
10
35
60
85
TEMPERATURE (°C)
JITTER vs. FREQUENCY
MAX9489 toc04
TYPICAL CLOCK WAVEFORMS
MAX9489 toc05
75
60
RMS PERIOD JITTER (ps)
A
45
30
B
15
0
25
43
61
79
97
115
133
10ns/div
A: 100MHz, 100mV/div
B: 25MHz, 100mV/div
FREQUENCY (MHz)
_______________________________________________________________________________________
5
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