FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50104-2E
MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
16M (×16) FLASH MEMORY &
2M (× 8) STATIC RAM
MB84VA2102
-10
/MB84VA2103
-10
s
FEATURES
• Power supply voltage of 2.7 to 3.6 V
• High performance
100 ns maximum access time
• Operating Temperature
–20 to +85°C
— FLASH MEMORY
• Minimum 100,000 write/erase cycles
• Sector erase architecture
One 8 K word, two 4 K words, one 16 K word, and thirty one 32 K words.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
MB84VA2102: Top sector
MB84VA2103: Bottom sector
• Embedded Erase
TM
Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready-Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low V
CC
write inhibit
≤
2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
Please refer to "MBM29LV160T/B" data sheet in detailed function
— SRAM
• Power dissipation
Operating : 35 mA max.
Standby : 50
µA
max.
• Power down features using CE1s and CE2s
• Data retention supply voltage: 2.0 V to 3.6 V
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
MB84VA2102
-10
/MB84VA2103
-10
s
PIN ASSIGNMENTS
(Top View)
A
6
5
4
3
2
1
CE1s
A
10
OE
A
11
A
13
WE
B
V
SS
DQ
5
DQ
7
A
8
A
17
V
CC
s
C
DQ
1
DQ
2
DQ
4
A
5
SA*
A
16
D
A
1
A
0
DQ
0
DQ
8
CEf
V
SS
E
A
2
A
3
A
6
DQ
3
DQ
10
DQ
9
F
A
4
A
7
A
18
DQ
12
V
CC
f
DQ
11
G
CE2s
RY/BY
RESET
A
12
DQ
6
DQ
13
H
A
9
A
14
A
15
A
19
DQ
15
/A
-1
DQ
14
*:
A
17
for SRAM
Table 1 Pin Configuration
Pin
A
0
to A
16
A
17
to A
19
SA
DQ
0
to DQ
7
DQ
8
to DQ
15
CEf
CE1s
CE2s
OE
WE
RY/BY
RESET
N.C.
V
SS
V
CC
f
V
CC
s
Function
Address Inputs (Common)
Address Input (Flash)
Address Input (SRAM)
Data Inputs/Outputs (Common)
Data Inputs/Outputs (Flash)
Chip Enable (Flash)
Chip Enable (SRAM)
Chip Enable (SRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Outputs (Flash)
Hardware Reset Pin/Sector Protection Unlock (Flash)
No Internal Connection
Device Ground (Common)
Device Power Supply (Flash)
Device Power Supply (SRAM)
Input/
Output
I
I
I
I/O
I/O
I
I
I
I
I
O
I
—
Power
Power
Power
3
MB84VA2102
-10
/MB84VA2103
-10
s
PRODUCT LINE UP
Flash Memory
Ordering Part No.
V
CC
= 3.0 V
+0.6 V
–0.3 V
SRAM
MB84VA2102-10/MB84VA2103-10
100
100
40
100
100
50
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
s
BUS OPERATIONS
Table 2 User Bus Operations
Operation (1), (3)
Full Standby
Output Disable
Read from Flash (2)
CEf
H
X
X
L
X
H
Write to Flash
Read from SRAM
Write to SRAM
Flash Hardware Reset
L
X
H
H
X
X
L
L
L
H
L
H
H
X
X
X
HIGH-Z
HIGH-Z
L
L
X
H
L
D
OUT
D
IN
HIGH-Z
HIGH-Z
H
H
L
X
H
L
D
IN
D
IN
H
X
H
L
X
X
L
H
D
OUT
D
OUT
H
H
H
HIGH-Z
HIGH-Z
H
CE1s
H
CE2s
X
X
X
HIGH-Z
HIGH-Z
H
OE
WE
DQ
0
to DQ
7
DQ
8
to DQ
15
RESET
Legend:
L = V
IL
, H = V
IH
, X = V
IL
or V
IH
. See DC Characteristics for voltage levels.
Notes:
1. Other operations except for indicated this column are inhibited.
2. WE can be V
IL
if OE is V
IL
, OE at V
IH
initiates the write operations.
3. Do not apply CEf = V
IL
, CE1s = V
IL
and CE2s = V
IH
at a time.
4
MB84VA2102
-10
/MB84VA2103
-10
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY
•One 8 K word, two 4 K words, one 16 K word, and thirty one 32 K words.
•Individual-sector, multiple-sector, or bulk-erase capability.
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
Sector Size
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
16K Words
4K Words
4K Words
8K Words
Address Range
00000H to 07FFFH
08000H to 0FFFFH
10000H to 17FFFH
18000H to 1FFFFH
20000H to 27FFFH
28000H to 2FFFFH
30000H to 37FFFH
38000H to 3FFFFH
40000H to 47FFFH
48000H to 4FFFFH
50000H to 57FFFH
58000H to 5FFFFH
60000H to 67FFFH
68000H to 6FFFFH
70000H to 77FFFH
78000H to 7FFFFH
80000H to 87FFFH
88000H to 8FFFFH
90000H to 97FFFH
98000H to 9FFFFH
A0000H to A7FFFH
A8000H to AFFFFH
B0000H to B7FFFH
B8000H to BFFFFH
C0000H to C7FFFH
C8000H to CFFFFH
D0000H to D7FFFH
D8000H to DFFFFH
E0000H to E7FFFH
E8000H to EFFFFH
F0000H to F7FFFH
F8000H to FBFFFH
FC000H to FCFFFH
FD000H to FDFFFH
FE000H to FFFFFH
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
Sector Size
8K Words
4K Words
4K Words
16K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
32K Words
Address Range
00000H to 01FFFH
02000H to 02FFFH
03000H to 03FFFH
04000H to 07FFFH
08000H to 0FFFFH
10000H to 17FFFH
18000H to 1FFFFH
20000H to 27FFFH
28000H to 2FFFFH
30000H to 37FFFH
38000H to 3FFFFH
40000H to 47FFFH
48000H to 4FFFFH
50000H to 57FFFH
58000H to 5FFFFH
60000H to 67FFFH
68000H to 6FFFFH
70000H to 77FFFH
78000H to 7FFFFH
80000H to 87FFFH
88000H to 8FFFFH
90000H to 97FFFH
98000H to 9FFFFH
A0000H to A7FFFH
A8000H to AFFFFH
B0000H to B7FFFH
B8000H to BFFFFH
C0000H to C7FFFH
C8000H to CFFFFH
D0000H to D7FFFH
D8000H to DFFFFH
E0000H to E7FFFH
E8000H to EFFFFH
F0000H to F7FFFH
F8000H to FFFFFH
MB84VA2102 Sector Architecture
MB84VA2103 Sector Architecture
5
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