SPANSION MCP
Data Sheet
TM
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50212-3E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM
CMOS
32M (×16) FLASH MEMORY &
16M (×16) SRAM Interface FCRAM
MB84VD22386EJ/VD22387EJ/VD22388EJ-85/90
MB84VD22396EJ/VD22397EJ/VD22398EJ-85/90
s
FEATURES
• Power Supply Voltage of 2.7 V to 3.1 V for FCRAM
• Power Supply Voltage of 2.7 V to 3.3 V for Flash
• High Performance
85 ns maximum access time (Flash)
85 ns maximum access time (FCRAM)
• Operating Temperature
–30
°C
to +85
°C
• Package 71-ball BGA
(Continued)
s
PRODUCT LINE-UP
Flash Memory
Power Supply Voltage (V)
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
V
CC
f* = 2.7 to 3.3
85
85
35
FCRAM
V
CC
s* = 2.7 to 3.1
85
85
50
*: Both V
CC
f and V
CC
s must be the same level when either part is being accessed.
s
PACKAGE
71-ball plastic BGA
(BGA-71P-M02)
Note : These guarantee both FCRAM and Flash at 85 ns Access Cycle.
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
1. FLASH MEMORY
• Simultaneous Read/Write Operations (Dual Bank)
Multiple devices available with different bank sizes
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
• Minimum 100,000 Write/Erase Cycles
• Sector Erase Architecture
Eight 4 K words and sixty three 32 K words.
Any combination of sectors can be concurrently erased. The devices also support full chip erase.
• Boot Code Sector Architecture
MB84VD22386EJ/VD22387EJ/VD22388EJ: Top sector
MB84VD22396EJ/VD22397EJ/VD22398EJ: Bottom sector
• Embedded Erase
TM
Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion
• Ready-Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode
When addresses remain stable, automatically switch themselves to low power mode.
• Hidden ROM (Hi-ROM) Region
64 Kbyte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC Input Pin
Allows protection of boot sectors at V
IL
, regardless of sector protection/unprotection status
(MB84VD22386EJ/VD22387EJ/VD22388EJ: SA69,SA70
MB84VD22396EJ/VD22397EJ/VD22398EJ: SA0,SA1)
Allows removal of boot sector protection at V
IH
.
At VACC, program time will reduce by 40%.
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Please Refer to “MBM29DL32XTE/BE” Data Sheet in Detailed Function
2. FCRAM
• Power Dissipation
Operating: 20 mA Max
Standby: 70
µA
Max
Power Down: 10
µA
Max
• Power Down Control by CE2s
• Byte Write Control: LBs (DQ
7
-DQ
0
), UBs (DQ
15
-DQ
5
)
• 4 Words Address Access Capability
2
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
s
PIN DESCRIPTIONS
Pin Name
A
19
to A
0
A
20
DQ
15
to DQ
0
CEf
CE1s
CE2s
OE
WE
RY/BY
UBs
LBs
RESET
WP/ACC
N.C.
V
SS
V
CC
f
V
CC
s
Input/Output
I
I
I/O
I
I
I
I
I
O
I
I
I
I
—
Power
Power
Power
Address Inputs (Common)
Address Input (Flash)
Data Inputs/Outputs (Common)
Chip Enable (Flash)
Chip Enable (FCRAM)
Chip Enable (FCRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Outputs (Flash) Open Drain Output
Upper Byte Control (FCRAM)
Lower Byte Control (FCRAM)
Hardware Reset Pin/Sector Protection Unlock (Flash)
Write Protect / Acceleration (Flash)
No Internal Connection
Device Ground (Common)
Device Power Supply (Flash)
Device Power Supply (FCRAM)
Function
4
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
