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IS61WV6416DBLL-10KI

产品描述Standard SRAM, 64KX16, 10ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, MS-027, SOJ-44
产品类别存储    存储   
文件大小738KB,共21页
制造商Integrated Silicon Solution ( ISSI )
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IS61WV6416DBLL-10KI概述

Standard SRAM, 64KX16, 10ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, MS-027, SOJ-44

IS61WV6416DBLL-10KI规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称Integrated Silicon Solution ( ISSI )
零件包装代码SOJ
包装说明SOJ, SOJ44,.44
针数44
Reach Compliance Codecompliant
ECCN代码3A991.B.2.B
最长访问时间10 ns
I/O 类型COMMON
JESD-30 代码R-PDSO-J44
长度28.58 mm
内存密度1048576 bit
内存集成电路类型STANDARD SRAM
内存宽度16
功能数量1
端子数量44
字数65536 words
字数代码64000
工作模式ASYNCHRONOUS
最高工作温度85 °C
最低工作温度-40 °C
组织64KX16
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码SOJ
封装等效代码SOJ44,.44
封装形状RECTANGULAR
封装形式SMALL OUTLINE
并行/串行PARALLEL
电源2.5/3.3 V
认证状态Not Qualified
座面最大高度3.76 mm
最大待机电流0.000055 A
最小待机电流2 V
最大压摆率0.055 mA
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)2.4 V
标称供电电压 (Vsup)3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子形式J BEND
端子节距1.27 mm
端子位置DUAL
宽度10.16 mm
Base Number Matches1

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IS61WV6416DALL/DALS
IS61WV6416DBLL/DBLS
IS64WV6416DBLL/DBLS
64K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM
FEATURES
HIGH SPEED: (IS61/64WV6416DALL/DBLL)
• High-speed access time: 8, 10, 12, 20 ns
• Low Active Power: 135 mW (typical)
• Low Standby Power: 12 µW (typical)
CMOS standby
LOW POWER: (IS61/64WV6416DALS/DBLS)
• High-speed access time: 25, 35 ns
• Low Active Power: 55 mW (typical)
• Low Standby Power: 12 µW (typical)
CMOS standby
• Single power supply
— V
dd
1.65V to 2.2V (IS61WV6416DAxx)
— V
dd
2.4V to 3.6V (IS61/64WV6416DBxx)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial and Automotive temperature support
• Lead-free available
JANUARY 2011
are high-speed, 1,048,576-bit static RAMs organized as
65,536 words by 16 bits. It is fabricated using
ISSI
's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields
high-performance and low power consumption devices.
DESCRIPTION
The
ISSI
IS61WV6416DAxx/DBxx and IS64WV6416DBxx
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be re-
duced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61WV6416DAxx/DBxx and IS64WV6416DBxx
are packaged in the JEDEC standard 44-pin TSOP Type
II, 44-pin 400-mil SOJ and 48-pin Mini BGA (6mm x
8mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A15
DECODER
64K x 16
MEMORY ARRAY
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
11/18/2010
1

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