CAT24C01B
1K-Bit Serial EEPROM
FEATURES
I
2-Wire Serial Interface
I
1.8 to 6.0Volt Operation
I
Low Power CMOS Technology
I
4-Byte Page Write Buffer
I
Self-Timed Write Cycle with Auto-Clear
I
1,000,000 Program/Erase Cycles
I
100 Year Data Retention
I
8-pin DIP, 8-pin SOIC, 8 pin TSSOP or 8-pin MSOP
I
Commercial, Industrial and Automotive
Temperature Ranges
I
"Green" Package Options Available
DESCRIPTION
The CAT24C01B is a 1K-bit Serial CMOS EEPROM
internally organized as 128 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces de-
vice power requirements. The CAT24C01B features a
4-byte page write buffer. The device operates via a 2-
wire serial interface and is available in 8-pin DIP, 8-pin
SOIC, 8-pin TSSOP or 8-pin MSOP.
PIN CONFIGURATION
DIP Package (P, L, GL)
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VCC
TEST
SCL
SDA
SOIC Package (J, W, GW)
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
MSOP Package (R, Z, GZ)
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VCC NC
TEST NC
SCL
NC
SDA VSS
TSSOP Package (U, Y, GY)
1
2
3
4
8
7
6
5
PIN FUNCTIONS
Pin Name
NC
SDA
SCL
V
CC
V
SS
i
D
c
s
n
o
i
t
VCC
TEST
SCL
SDA
u
n
VCC
VSS
SDA
BLOCK DIAGRAM
EXTERNAL LOAD
d
e
a
P
XDEC
t
r
DOUT
ACK
SENSE AMPS
SHIFT REGISTERS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
START/STOP
LOGIC
VCC
TEST
SCL
SDA
E
2
PROM
EEPROM
CONTROL
LOGIC
DATA IN STORAGE
Function
No Connect
Serial Data/Address
SCL
STATE COUNTERS
HIGH VOLTAGE/
TIMING CONTROL
Serial Clock
+1.8V to +6.0V Power Supply
Ground
Test Input (GND, V
CC
or
Floating)
TEST
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1081, Rev. E
CAT24C01B
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
........... –2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) .................................. 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min
1,000,000
100
2000
100
Max
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Symbol
I
CC
I
SB(5)
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OL2
Parameter
Power Supply Current
Standby Current (V
CC
= 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
I/O(3)
C
IN(3)
Test
Max
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL, WP)
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(5) Maximum standby current (I
SB
) = 10µA for the Automotive and Extended Automotive temperature range.
i
D
Input High Voltage
Output Low Voltage (V
CC
= 3.0V)
Output Low Voltage (V
CC
= 1.8V)
c
s
n
o
i
t
Min
–1
u
n
Limits
Typ
d
e
Max
3
1
10
10
0.4
0.5
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
a
P
t
r
Units
mA
µA
µA
µA
V
V
V
V
Test Conditions
f
SCL
= 100 KHz
V
IN
= GND or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
V
CC
x 0.3
V
CC
+ 0.5
V
CC
x 0.7
I
OL
= 3 mA
I
OL
= 1.5 mA
Doc. No. 1081, Rev. E
2
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C01B
A.C. CHARACTERISTICS
V
CC
= +1.8V to +6.0V, C
L
=1TTL Gate and 100pF (unless otherwise specified).
Read & Write Cycle Limits
Symbol
Parameter
1.8V, 2.5V
Min
F
SCL
T
I(1)
t
AA
t
BUF(1)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(1)
t
F(1)
t
SU:STO
t
DH
Clock Frequency
Noise Suppression Time
Constant at SCL, SDA Inputs
SCL Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
4.7
4
4.7
4
Max
100
100
3.5
1.2
4.5V-5.5V
Min
Max
400
100
Units
Stop Condition Setup Time
Data Out Hold Time
Power-Up Timing
(1)(2)
Symbol
t
PUR
t
PUW
Write Cycle Limits
Symbol
t
WR
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
i
D
c
s
Power-up to Read Operation
Power-up to Write Operation
n
o
Parameter
i
t
u
n
0
250
4.7
100
4.7
1
d
e
1.2
0.6
0.6
0
100
0.6
100
Max
1
1
0.6
a
P
1
0.3
300
t
r
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
300
Units
ms
ms
Parameter
Min
Typ
Max
10
Units
ms
Write Cycle Time
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its input.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1081, Rev. E
CAT24C01B
FUNCTIONAL DESCRIPTION
The CAT24C01B uses a 2-wire data transmission pro-
tocol. The protocol defines any device that sends data to
the bus to be a transmitter and any device receiving data
to be a receiver. Data transfer is controlled by the Master
device which generates the serial clock and all START
and STOP conditions for bus access. The CAT24C01B
operates as a Slave device. Both the Master and Slave
devices can operate as either transmitter or receiver, but
the Master device controls which mode is activated.
SDA:
Serial Data/Address
The CAT24C01B bidirectional serial data/address pin is
used to transfer data into and out of the device. The SDA
pin is an open drain output and can be wired with other
open drain or open collector outputs.
2-WIRE BUS PROTOCOL
The following defines the features of the 2-wire bus
protocol:
PIN DESCRIPTIONS
SCL:
Serial Clock
The CAT24C01B serial clock input pin is used to clock
all data transfers into or out of the device. This is an input
pin.
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
Figure 1. Bus Timing
tF
tLOW
SCL
tSU:STA
tHD:STA
tHIGH
tLOW
tR
tHD:DAT
SDA IN
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
Figure 3. Start/Stop Timing
i
D
c
s
8TH BIT
BYTE n
SDA
SCL
n
o
ACK
tAA
i
t
u
n
tSU:DAT
tDH
tWR
d
e
a
P
t
r
tSU:STO
tBUF
5020 FHD F03
STOP
CONDITION
START
CONDITION
ADDRESS
5020 FHD F04
5020 FHD F05
START BIT
Doc. No. 1081, Rev. E
STOP BIT
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C01B
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24C01B monitors the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24C01B responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
When the CAT24C01B is in a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this acknowl-
edge, the CAT24C01B will continue to transmit data. If
no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
(with the R/W bit set to zero) to the Slave device. After the
Slave generates an acknowledge, the Master sends the
byte address that is to be written into the address pointer
of the CAT24C01B. After receiving another acknowl-
edge from the Slave, the Master device transmits the
data byte to be written into the addressed memory
location. The CAT24C01B acknowledge once more and
the Master generates the STOP condition, at which time
the device begins its internal programming cycle to
nonvolatile memory. While this internal cycle is in
progress, the device will not respond to any request from
the Master device.
Page Write
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
Figure 4. Acknowledge Timing
i
D
c
s
SCL FROM
MASTER
n
o
START
i
t
1
u
n
The CAT24C01B writes up to 4 bytes of data in a single
write cycle, using the Page Write operation. The Page
Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to 3 additional bytes. After each byte has been
transmitted the CAT24C01B will respond with an ac-
knowledge, and internally increment the low order ad-
dress bits by one. The high order bits remain un-
changed.
If the Master transmits more than 4 bytes prior to sending
the STOP condition, the address counter ‘wraps around,’
and previously transmitted data will be overwritten.
Once all 4 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24C01B in a single write cycle.
d
e
a
P
t
r
Note: Catalyst Semiconductor does program all "1" data
into the entire memory array prior to shipping our
EEPROM products.
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
5020 FHD F06
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 1081, Rev. E
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
