without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
06/25/02
1
IS25C32-2/3
IS25C64-2/3
ISSI
14-pin TSSOP
®
PIN CONFIGURATION
8-Pin DIP and SOIC
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
NC
NC
NC
WP
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
HOLD
NC
NC
NC
SCK
SI
PIN DESCRIPTIONS
PIN DESCRIPTIONS
CS
SCK
SI
SO
GND
V
CC
WP
HOLD
NC
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power
Write Protect
Suspends Serial Input
No Connect
Serial Clock (SCK)
- This pin is used to synchronize the
communication between the microcontroller and the
IS25C64, IS25C32. Op-codes, byte addresses, or data
present on the SI pin and latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge of
the SCK for SPI modes (0,0 & 1,1).
Serial Data Input (SI)
- The SI pin is used to input all op-
codes, byte addresses, and data to be written to the
device. Input data is latched on the rising edge of the
serial clock for SPI modes (0,0 & 1,1).
Serial Data Output (SO)
- The SO pin is used to transfer
data out of the device. During a read cycle, data is shifted
out on the falling edge of the serial clock for SPI modes (0,0
& 1,1).
Chip Select (
CS
):
When the
CS
pin is low, the device is
enabled. When the
CS
pin is high the device is disabled.
CS
high takes the SO output pin to high impedance and
forces the devices into a Standby Mode (unless an
internal write operation is underway). The devices draws
zero current in the Standby mode. A high-to-low transition
on
CS
is required prior to any sequence being initiated. A
low-to-high transition on
CS
after a valid write sequence is
what initiates an internal write cycle.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
06/25/02
IS25C32-2/3
IS25C64-2/3
PIN DESCRIPTIONS Continued:
Write Protect (
WP
)
- The
WP
Pin will allow normal read/
write operations when held high. When
WP
is tied low and
the WPEN bit in the status register is set to "1", all write
operations to the status register are inhibited.
WP
going
low while CS is still low will interrupt a write to the status
register. If the internal write cycle has already been
initiated,
WP
going low will have no effect on any write
operation to the status register. The
WP
pin function is
blocked when the WPEN bit is set to 0. Figure 10
illustrates the
WP
timing sequence during a write opera-
tion.
Hold (
HOLD
):
The
HOLD
pin is used to pause transmis-
sion to the device while in the middle of a serial sequence
without having to retransmit entire sequence at a later
time. To pause,
HOLD
must be brought low while SCK is
low. The SO pin is in a high impedance state during the
time the part is paused, and transition on the SI pins will
be ignored. To resume communication,
HOLD
is brought
high, while SCK is low. (HOLD should be held high any
time this function is not being used.)
HOLD
may be tied
high directly to Vcc or tied to Vcc through a resistor. The
HOLD
Timing Diagram illustrates hold timing sequence.
ISSI
SERIAL INTERFACE DESCRIPTION
MASTER:
This device that generates the serial clock.
®
SLAVE:
Because the Serial Clock pin (SCK) is always an
input, the device always operates as a slave.
MSB:
The Most Significant Bit (MSB) is the first bit
transmitted and received.
SERIAL OP-CODE:
After the device is selected with CS
going low, the first byte will be received. This byte contains
the op-code that defines the operations to be performed.
INVALID OP-CODE:
If an invalid op-code is received, no
data will be shifted into the device, and the serial output pin
(SO) will remain in a high impedance state until the falling
edge of CS is detected again. This will reinitialize the serial
communications.
BLOCK DIAGRAM
VCC
GND
STATUS
REGISTER
8192 x 8/4096 x 8
MEMORY ARRAY
DATA
REGISTER
SI
MODE
DECODE
LOGIC
ADDRESS
DECODER
OUTPUT
BUFFER
CS
WP
SCK
CLOCK
so
HOLD
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
06/25/02
3
IS25C32-2/3
IS25C64-2/3
FUNCTIONAL DESCRIPTIONS
The IS25C32/64 utilizes an 8-bit instruction register. The
list of instructions and their operation codes are contained
in Table 1. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to low
CS transition.
ISSI
Bit
Bit 0 (RDY)
®
Table 3. Read Status Register Bit Definition
Definition
Bit 0 = 0 (RDY) indicates the device is
READY. Bit 0 = 1 indicates the write
cycle is in progress.
Bit 1 = 0 indicates the device is not
WRITE ENABLED. Bit 1 = 1 indicates
the device is WRITE ENABLED.
See Table 4
See Table 4
Bit 1(WEN)
Table 1. Instruction Set
Name
WREN
WRDI
RDSR
WRSR
READ
WRITE
Instruction
Format
Bit 2 (BPO)
Operation
Bit 3 (BP1)
0000 X110
Set Write Enable Latch
0000 X100
Reset Write Enable Latch
0000 X101
Read Status Register
0000 X001
Write Status Register
0000 X011 Read Data from Memory Array
0000 X010
Write Data to Memory Array
Bits 4 - 6 are 0s when the device is not an internal write cycle.
Bits 7 (WPEN) See Table 5.
Bits 0-7 are 1s during an internal write cycle.
WRITE ENABLE (WREN):
This device will power-up in
the write disable state when VCC is applied. All program-
ming instructions must therefore be preceded by a Write
Enable instruction.
WRITE DISABLE (WRDI):
To protect the device against
inadvertent writes, the Write Disable instruction disables
all programming modes. The WRDI instruction is indepen-
dent of the status of the
WP
pin.
READ STATUS REGISTER (RDSR):
The Read Status Register instruction provides access to
the status register. The READY/BUSY and Write Enable
status of the device can be determined by the RDSR
instruction. Similarly, the Block Write Protection bits
indicate the extent of protection employed. These bits are
set by using the WRSR instruction.
WRITE STATUS REGISTER (WRSR):
The WRSR in-
struction allows the user to select one of four levels of
protection. The device is divided into four array seg-
ments. One quarter (1/4), one half (1/2) or all of the
memory segments can be protected. Any of the data
within any selected segment will therefore be READ only.
The block write protection levels and corresponding
status register control bits are shown in Table 4.
The three bits, BP, BP1 and WPEN are nonvolatile
cells that have the same properties and functions as
the regular memory cells (e.g. WREN, twc, RDSR).
Table 4. Status Register Format
Status
Register
Bits
Level
BP1
0
0
1
1
BP0
0
1
0
1
0
1(1/4)
2(1/2)
3(All)
Array Addresses Protected
IS25C32
None
0C00
-0FFF
0800
-0FFF
0000
-0FFF
IS25C64
None
1800
-1FFF
1000
-1FFF
0000
-1FFF
Table 2. Status Register Format
Bit 7
WPEN
Bit 6 Bit 5 Bit 4
x
x
x
Bit 3 Bit 2 Bit1 Bit 0
BP1 BP0 WEN
RDY
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
06/25/02
IS25C32-2/3
IS25C64-2/3
The WRSR instruction also allows the user to enable or
disable the write protect (WP) pin through the use of the
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