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IS65WV12816ALL-70TA3

产品描述128KX16 STANDARD SRAM, 70ns, PDSO44, PLASTIC, TSOP2-44
产品类别存储    存储   
文件大小100KB,共19页
制造商Integrated Silicon Solution ( ISSI )
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IS65WV12816ALL-70TA3概述

128KX16 STANDARD SRAM, 70ns, PDSO44, PLASTIC, TSOP2-44

IS65WV12816ALL-70TA3规格参数

参数名称属性值
是否无铅含铅
是否Rohs认证不符合
厂商名称Integrated Silicon Solution ( ISSI )
零件包装代码TSOP2
包装说明PLASTIC, TSOP2-44
针数44
Reach Compliance Codecompliant
ECCN代码3A991.B.2.A
最长访问时间70 ns
I/O 类型COMMON
JESD-30 代码R-PDSO-G44
JESD-609代码e0
长度18.415 mm
内存密度2097152 bit
内存集成电路类型STANDARD SRAM
内存宽度16
湿度敏感等级3
功能数量1
端子数量44
字数131072 words
字数代码128000
工作模式ASYNCHRONOUS
最高工作温度125 °C
最低工作温度-40 °C
组织128KX16
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码TSOP2
封装等效代码TSOP44,.46,32
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE
并行/串行PARALLEL
峰值回流温度(摄氏度)NOT SPECIFIED
电源1.8/2 V
认证状态Not Qualified
筛选级别AEC-Q100
座面最大高度1.2 mm
最大待机电流0.000065 A
最小待机电流1.2 V
最大压摆率0.02 mA
最大供电电压 (Vsup)2.2 V
最小供电电压 (Vsup)1.65 V
标称供电电压 (Vsup)1.8 V
表面贴装YES
技术CMOS
温度等级AUTOMOTIVE
端子面层Tin/Lead (Sn/Pb)
端子形式GULL WING
端子节距0.8 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度10.16 mm
Base Number Matches1

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IS65WV12816ALL
IS65WV12816BLL
128K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access time: 55ns, 70ns
• CMOS low power operation:
36 mW (typical) operating
9 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply:
1.65V to 2.2V V
DD
(65WV12816ALL)
2.5V to 3.6V V
DD
(65WV12816BLL)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• 2CS Option Available
• Temperature Offerings:
Option A: 0 to 70
o
C
Option A1: –40 to +85 C
o
ISSI
Option A2: –40 to +105
o
C
Option A3: –40 to +125
o
C
®
PRELIMINARY INFORMATION
FEBRUARY 2003
DESCRIPTION
The
ISSI
IS65WV12816ALL/ IS65WV12816BLL are high-
speed, 2M bit static RAMs organized as 128K words by 16
bits. It is fabricated using
ISSI
's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-
performance and low power consumption devices.
When
CS1
is HIGH (deselected) or when CS2 is LOW
(deselected) or when
CS1
is LOW, CS2 is HIGH and both
LB
and
UB
are HIGH, the device assumes a standby mode
at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE)
controls both writing and reading of the memory. A
data byte allows Upper Byte
(UB)
and Lower Byte (LB)
access.
The IS65WV12816ALL and IS65WV12816BLL are packged
in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and
44-Pin TSOP (TYPE II).
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 16
MEMORY ARRAY
V
DD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CS2
CS1
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00D
02/05/03
1

 
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