Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETER
DC Supply Current
OSC Source Current
OSC Sink Current
OSC Threshold Voltage
OSC Trigger Voltage
TRIGGER Input Leak Current
TORQUE Input Leak Current
DELAY Current at 1V
DELAY Current at 2V
DELAY Threshold Voltage
DRAIN Input Resistance
DRAIN Current
GATE Output Source Current
GATE Output Voltage
GATE Output Slew Rate
V
DD
= 7.5V, Figure 1 Test Circuit, Table 1 Conditions, T
A
= +25
o
C Unless Otherwise Specified
SYMBOL
I
DD
+I
OSC
-I
OSC
V
OSC(TH)
V
OSC(TR)
I
TRIGGER
I
TORQUE
I
DELAY1
I
DELAY2
V
DELAY(TH)
R
DRAIN
I
DRAIN
I
GATE
V
GATE
V
GATE(S/R)
FP/DC
Measured in Typical Application Circuit,
Duty Cycle = 50%, See Figure 2
Gate Duty Cycle = 50%;
V
TORQUE
= GND; V
DRAIN
= V
GATE;
DELAY =10kΩ to GND, Refer to Figure 1
for the Test circuit and Timing Diagram of
the DELAY Output Pulse Frame.
T
A
= 25
o
C
T
A
= -40
o
C
T
A
= 85
o
C
TEST CONDITIONS
MIN
0.1
19
-32
4.75
2.30
-
-
1.5
1
1.8
150
1
10
6.5
-
TYP
1.2
25
-25
4.95
2.45
0.02
0.02
3.4
32
1.9
260
1.7
18
7.4
10
MAX
3.1
32
-19
5.25
2.65
1.5
1.5
6
50
2
350
4.6
-
-
-
UNITS
mA
µA
µA
V
V
µA
µA
µA
mA
V
kΩ
mA
mA
V
V/µs
DELAY Output Framed Pulse
Duty Cycle
DELAY Output Framed Pulse De-
lay, V
GATE
to V
DELAY
Typical Oscillator Frequency
-
44
-
%
FP/DLY
-
-
-
-
3
5
7.2
3.6
-
-
-
-
%
kHz
kHz
kHz
f
OSC
NOTES:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
3
HIP9021
V
DD
15KΩ
2V
1V
2V
5V
2V
5V
5V
7.5V
V
DRAIN
1nF
1
DRAIN
5
+
-
CONTROL
& LOGIC
GC
-
+
7
GATE
4
OSC
HIP9021
GND
3
OSC
V
OSC
V
GATE
10nF
3.75V
2.5V
5V
1nF
V
DD
8
+
10µF
0.01µF
6
V
DELAY
1V
2V
10K
R
D
V
TORQUE
1nF
V
TRIGGER
22nF
DELAY
TORQUE
2
TRIGGER
V
GATE
V
DD
GND
GATE PULSE WIDTH
V
DELAY
FRAMED PULSE WIDTH
FRAMED PULSE DELAY
1V
GND
NOTE: The timing diagrams relate to the delay output framed pulse and show the time duration of the delay pulse “framed” inside of the gate
pulse. The framed pulse duty cycle and delay, in percent, are measured in reference to the gate pulse which is set at 50% duty cycle. The
Delay output framed pulse delay is one-half of the difference of the gate pulse width minus delay output framed pulse width.
FIGURE 1. ELECTRICAL CHARACTERISTICS TEST CIRCUIT FOR SIGNAL FUNCTIONS OF THE HIP9021
TABLE 1. SWITCH POSITIONS OF FIGURE 1 FOR ELECTRICAL CHARACTERISTIC TESTING
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
