CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
2. Fault capability of the J1850 Bus Transceiver includes reverse battery, load dump and latch-up tolerance to
±200mA
on any terminal. The
Short Term Power Supply Voltage capability is 35V for a maximum of 1s. Continued operation at this voltage may cause thermal shutdown.
3. Transient Susceptibility Bus and Battery Pins Per SAE J1113, Aug 1987, Figures 7 Test Pulses 1, 2, 3A and 3B at -50V, +100V and
±200V
respectively.
4. ESD Conditions - SAE J1113; Aug 1987. BUS OUT & BATTERY Pins: Air Gap and Direct Contact Discharge; R = 2kΩ, C = 150pF
All Other Pins: Direct Contact Discharge; R = 1.5kΩ, C = 100pF
Electrical Specifications
9.0V
≤
V
BATT
≤
16V; R
S
= 56.2kΩ
±1%;
except as noted, R
BS
= 500Ω to 1500Ω and
τ
= R
BS
C
BS
= 5µs.
All voltages are measured with respect to ground and the T
A
Range of -40
o
C to 125
o
C shall not be
exceeded during test unless otherwise specified. For test detail, refer to the Block Diagram, Figures 3
and 4 Test Circuits and Figures 5 and 6 Waveforms.
SYMBOL
I
BATT
V
BATT
I
BATT(SG)
I
BATT(SB)
TEST CONDITIONS
BUS OUT Open; No Bus Signal;
V
BATT
= 12.6V; V
TX
Low
(Note 5)
BUS OUT Short to GND, V
TX
High
BUS OUT to V
BATT
; I
BO
= 0 mA
V
TX
High
V
TX
Low
T
SD
T
SDHYS
I
TX
V
IL
V
IH
C
TX
V
BOH
V
BOL
V
BOH(PSL)
I
BO_LIMIT
V
TX
High
Bus Load, R
BS
= 1.5kΩ; V
TX
Low
6V
≤
V
BATT
<
9V; V
TX
High
-20V
≤
V
BUS OUT
<
[V
BOH
(Measured) - 0.8V];
V
TX
High
(Note 6)
(Note 6)
MIN
90
6
20
2
90
150
5
TYP
200
-
-
-
-
-
10
MAX
350
24
50
8
350
170
15
UNITS
µA
V
mA
mA
µA
o
C
o
C
PARAMETER
Idle Supply Current
Operating Voltage Range
Supply Current,
BUS OUT Short to GND
Supply Current,
BUS OUT Short to BATT
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
TX CMOS/TTL INPUT WITH/PULL DOWN
Input Bias Current, TX
Input Low Voltage
Input High Voltage
Input Capacitance
BUS OUT
BUS OUT High Voltage
BUS OUT Low Voltage
BUS OUT Voltage, Low Battery
Source Current, Bus Low
BUS OUT During LOOPBACK
6.6
-
Note
13
-20
-
-
-
-
8.5
0.1
8.5
V
V
V
V
TX
= 7V; (Note 7)
20
-
2.0
2
-
-
-
-
38
0.8
-
5
µA
V
V
pF
-
-
-42
1
mA
V
V
LOOPBACK
LB EN Low, V
TX
High
3
HIP7020
Electrical Specifications
9.0V
≤
V
BATT
≤
16V; R
S
= 56.2kΩ
±1%;
except as noted, R
BS
= 500Ω to 1500Ω and
τ
= R
BS
C
BS
= 5µs.
All voltages are measured with respect to ground and the T
A
Range of -40
o
C to 125
o
C shall not be
exceeded during test unless otherwise specified. For test detail, refer to the Block Diagram, Figures 3
and 4 Test Circuits and Figures 5 and 6 Waveforms.
(Continued)
SYMBOL
V
dB_LIMIT
I
BO_LEAK
0V
≤
V
BUS OUT
≤
20V; 0V
≤
V
BATT
≤
0.8V;
-0.3V
≤
V
TX
≤
7V
-20V
≤
V
BUS OUT
≤
0V; 0V
≤
V
BATT
≤
0.8V;
-0.3V
≤
V
TX
≤
7V
V
BOH
<
V
BUS OUT
≤
20V; 6V
≤
V
BATT
≤
16V;
2V
≤
V
TX
≤
7V
0V
≤
V
BUS OUT
≤
20V; 6V
≤
V
BATT
≤
16V;
-0.3V
≤
V
TX
≤
0.8V
-20V
≤
V
BUS OUT
<
0V; 9.5V
≤
V
BATT
≤
16V;
-0.3V
≤
V
TX
≤
0.8V
V
GND
≤
V
BUS OUT
<
20V; 0V
≤
V
BATT
≤
16V;
-0.3V
≤
V
TX
≤
7V; 0V
≤
(V
BATT
- V
GND
)
≤
0.8V
-20V
≤
V
BUS OUT
≤
V
GND
; 0V
≤
V
BATT
≤
16V;
-0.3V
≤
V
TX
≤
7V; 0V
≤
(V
BATT
- V
GND
)
≤
0.8V
t
DTXHBO
,
t
DTXLBO
t
r
, t
f
N
R
N
I
V
BIH
I
BIN
C
BIN
V
IL
I
RX
I
RX(LK)
t
DRXON
,
t
DRXOFF
V
IL
V
IH
I
LB
t
DLBON
,
t
DLBOFF
t
D(LH)
,
t
D(HL)
V
LB
= 7V; (Note 9)
V
LB
Low; Toggle TX; Meas. RX
V
TX
High; Toggle LB EN; Meas. BUS OUT
I
RX
= 1.6mA
V
RX
= 5V (Note 10)
V
RX
= 5V, R
D
= 10kΩ; V
BUSIN
Low
Measured from BUS IN Threshold Voltage
-20V
≤
V
BUS IN
≤
20V
R
S
= 56.2kΩ; V
BUS OUT
= 3.875V (Note 8)
R
S
= 56.2kΩ; Measured on BUS OUT between 1.5V
and 6.25V (Note 8)
f
R
= 30Hz to 250kHz; V
BATT
to BUS OUT
f
I
= 0.25MHz to 200MHz; V
BATT
to BUS OUT
TEST CONDITIONS
MIN
-60
-10
-100
-10
-10
-3000
-10
-100
9
11
20
20
3.6
-5
10
0.01
2
-10
1
TYP
-
-
-
-
-
-
-
-
16
16
-
-
-
-
-
-
5
-
-
MAX
-
10
10
10
10
10
10
10
23
19
-
-
4.15
5
20
0.4
8
10
3
UNITS
dBV
µA
µA
µA
µA
µA
µA
µA
µs
µs
dB
dB
V
µA
pF
V
mA
µA
µs
PARAMETER
Bus Emissions Voltage Output
BUS OUT Leakage Currents
Battery Low/Off1
Battery Low/Off2
Bus High
TX Low1
TX Low2
With Loss of Ground1 (Note 11)
With Loss of Ground2 (Note 11)
TX to BUS OUT Propagation
Delays
BUS OUT Transition Times,
Rise and Fall
BUS OUT Noise Rejection
BUS OUT RF Isolation
BUS IN
Input Threshold Voltage
Input Bias Current
Input Capacitance
RX OUTPUT
Output Voltage, Low
Output Current
Output Leakage Current
Receive Propagation Delay
LB EN CMOS/TTL INPUT WITH/PULL DOWN
Input Low Voltage
Input High Voltage
Input Bias Current
TX To RX Turn ON, OFF;
Delay In Loop-Back Mode
LB EN Turn ON, OFF;
TX to BUS OUT
-
2.0
5
12
1
-
-
-
-
-
0.8
-
12
26
10
V
V
µA
µs
µs
NOTES:
5. In the operating voltage range from 6V to 8.5V the BUS OUT, V
BOH
is limited by the low power supply. In the operating voltage range
from 16V to 24V the maximum bus load is limited by the package power dissipation ratings.
6. Over-temperature shutdown with hysteresis is incorporated to protect the IC under system failure conditions.
7. Measured Current into the TX terminal is determined by Pull-Down Current Sink.
8. Propagation Delay limits are measured at the 3.875V level on BUS OUT. Rise and Fall Times are measured between 1.5V and 6.25V on
the BUS OUT terminal.
9. Measured Current into the LB EN terminal is determined by Pull-Down Current Sink.
10. The I
RX
Output Current test parameter defines Short Circuit protection limits.
11. Loss of Ground refers to loss of module (node) Ground which results in a voltage between the Battery and IC Ground of less than 0.8V.
For voltage between Battery and Ground above 0.8V, the Transceiver Bus Output may become active. The module circuit in Figure 3 is
used to measure the Loss of Ground leakage.
12. Unless otherwise noted, all Electrical Specification test conditions are as shown in Figure 4.
13. The lower limit is 6.6V or V
BATT
- 1.7V, whichever is less.
4
HIP7020
Test Circuits
V
BATT
510
0.1µF
10
100
0.1µF
10K
5.1V
TX
LB EN
RX
BATT
BUS OUT
BUS IN
GND
µA
500
15K
0.01µF
R/F
56.2K
±1%
SW
FIGURE 3. LOSS OF GROUND LEAKAGE TEST CIRCUIT
V
BATT
V
TX
LOW = 0V
V
TX
HIGH = 5V
TX
I
STX
R/F
R
S
56.2K
±1%
LB EN
5V
I
SLB
R
D
5K
RX
V
REF
TRANSMIT WAVEFORM
PROCESSING/SHAPING
VOLTAGE TO
CURRENT
CONVERTER
BATT
GND
DIAGNOSTIC
LOOP-BACK
MODE SW
†
Q1
BUS OUT
R
E
I
BO
10
R
F
15K
R
BS
V
BO
C
BS
†
SWITCH SHOWN
IN NORMAL MODE
BUS RECEIVER AND
VOLTAGE COMPARATOR
FILTER
BUS IN
R
BS
= 500Ω TO 1500Ω
τ
= R
BS
C
BS
≅
5µs
FIGURE 4. ELECTRICAL SPECIFICATION TEST CIRCUIT
HIP7020 Signal Interface
The HIP7020 is a member of the Intersil family of low cost
multiplexed wiring ICs. As a Bus Transceiver IC, it interfaces
the module and system control logic to the vehicle signal bus
wiring. The integrated functions of the Bus Transceiver serve
as an interface for a “Class B” multiplexed communications
network. The TX digital interface is designed to accept
CMOS/TTL logic levels and convert them to the appropriate
J1850 analog serial data levels. This is accomplished using
an internally generated reference waveform and voltage
driver with a controlled current source to supply an analog
signal output to the J1850 bus load of 500Ω (typical).
Because of the special wave shaping used to control the
J1850 bus waveform, it is regarded as an analog signal.
In the receive mode the incoming bus analog signals are input
to the receiver at the BUS IN terminal. The bus data is
converted to logic information by comparing it to an on-chip
reference voltage. The received signal is provided as digital
output from an open collector transistor driver at the
RX output.
In the transmit mode a CMOS/TTL digital signal is received
at the TX input. It is then rise and fall time controlled, wave
shaped and level adjusted. A voltage controlled current
driver circuit transmits the signal from the BUS OUT terminal
to the J1850 Bus with current limiting protection.
Functional Blocks
The Bus Transceiver IC functional blocks, as shown in the
Block Diagram, are as follows:
TX BUF (Transmit Input Buffer Interface)
The TX Buffer input function is a data interface to the wave-
shaper reference circuit. The CMOS/TTL logic levels to be
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