ispLSI
®
1024 Device Datasheet
June 2010
All Devices Discontinued!
Product Change Notification (PCN) #09-10 has been issued to discontinue all devices in
this data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
ispLSI 1024
Ordering Part Number
ispLSI 1024-60LJ
ispLSI 1024-80LJ
ispLSI 1024-90LJ
ispLSI 1024-60LJI
ispLSI 1024-60LT
ispLSI 1024-80LT
ispLSI 1024-90LT
ispLSI 1024-60LTI
Product Status
Reference PCN
Discontinued
PCN#09-10
5555 N.E. Moore Ct.
Hillsboro, Oregon 97124-6421 Phone (503) 268-8000
Internet: http://www.latticesemi.com
FAX (503) 268-8347
ispLSI 1024
®
In-System Programmable High Density PLD
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— High-Speed Global Interconnect
— 4000 PLD Gates
— 48 I/O Pins, Six Dedicated Inputs
— 144 Registers
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Fast Random Logic
— Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
—
f
max
= 90 MHz Maximum Operating Frequency
—
f
max
= 60 MHz for Industrial and Military/883 Devices
—
t
pd
= 12 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E
2
CMOS Technology
— 100% Tested
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
unctional
Block Diagram
A0
C7
C6
C5
C4
C3
C2
C1
C0
Output Routing Pool
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
A2
A3
A4
A5
A6
A7
Logic
D Q
A1
Array
D Q
GLB
D Q
Global Routing Pool (GRP)
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool
CLK
0139-A-isp
Description
The ispLSI 1024 is a High-Density Programmable Logic
Device containing 144 Registers, 48 Universal I/O pins,
six Dedicated Input pins, four Dedicated Clock Input pins
and a Global Routing Pool (GRP). The GRP provides
complete interconnectivity between all of these elements.
The ispLSI 1024 features 5-Volt in-system programma-
bility and in-system diagnostic capabilities. It is the first
device which offers non-volatile reprogrammability of the
logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 1024 device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. C7 (see figure 1). There are a total of 24 GLBs in the
ispLSI 1024 device. Each GLB has 18 inputs, a program-
mable AND/OR/XOR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
other GLB on the device.
Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
February 1999
1024_06
1
Output Routing Pool
D Q
Specifications
ispLSI 1024
Functional Block Diagram
Figure 1.ispLSI 1024 Functional Block Diagram
RESET
Generic
Logic Blocks
(GLBs)
IN 5
IN 4
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
C7
I/O 0
I/O 1
I/O 2
I/O 3
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
A0
C6
C5
C4
C3
C2
C1
C0
A1
A2
A3
A4
A5
A6
A7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
SDI/IN 0
SDO/IN 1
Input Bus
Global
Routing
Pool
(GRP)
B0
B1
B2
B3
B4
B5
B6
B7
Megablock
Output Routing Pool (ORP)
Input Bus
Clock
Distribution
Network
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
ispEN
SCLK/IN 2
MODE/IN 3
I/O I/O I/O I/O
16 17 18 19
I/O I/O I/O I/O
20 21 22 23
I/O I/O I/O I/O
24 25 26 27
I/O I/O I/O I/O
28 29 30 31
Y Y Y Y
0 1 2 3
lnput Bus
I/O 4
I/O 5
I/O 6
I/O 7
Output Routing Pool (ORP)
Output Routing Pool (ORP)
0139D_1024.eps
The device also has 48 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered in-
put, latched input, output or
bi-directional
I/O pin with 3-state control. Additionally, all outputs are
polarity selectable, active high or active low. The signal
levels are TTL compatible voltages and the output drivers
can source 4 mA or sink 8 mA.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected
to a set of 16 universal I/O cells by the ORP. The I/O cells
within the Megablock also share a common Output
Enable (OE) signal. The ispLSI 1024 device contains
three of these Megablocks.
The GRP has as its inputs the outputs from all of the GLBs
and all of the inputs from the bi-directional I/O cells. All of
these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1024 device are selected using the
Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (B4 on the ispLSI
1024 device). The logic of this GLB allows the user to
create an internal clock from a combination of internal
signals within the device.
2
Specifications
ispLSI 1024
Absolute Maximum Ratings
1
Supply Voltage V
cc
.................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to V
CC
+1.0V
Off-State Output Voltage Applied ..... -2.5 to V
CC
+1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
Max. Junction Temp. (T
J
) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL
PARAMETER
MIN.
4.75
4.5
4.5
0
MAX.
5.25
5.5
5.5
0.8
UNITS
Commercial
T
A
= 0°C to +70°C
V
CC
V
IL
V
IH
Supply Voltage
Industrial
T
A
= -40°C to +85°C
V
Military/883
T
C
= -55°C to +125°C
Input Low Voltage
V
V
Input High Voltage
2.0
Vcc
+ 1
Table 2- 0005Aisp w/mil.eps
Capacitance (T
A
=25
o
C, f=1.0 MHz)
PARAMETER
SYMBOL
MAXIMUM
1
8
UNITS
pf
TEST CONDITIONS
C
1
C
2
Dedicated Input Capacitance
Commercial/Industrial
Military
V
CC
=5.0V, V
IN
=2.0V
V
CC
=5.0V, V
IN
=2.0V
10
pf
I/O and Clock Capacitance
10
pf
V
CC
=5.0V, V
I/O
, V
Y
=2.0V
Table 2- 0006
1
.
Guaranteed but not 100% tested.
Data Retention Specifications
PARAMETER
Data Retention
MINIMUM
20
10000
MAXIMUM
—
—
UNITS
Years
Erase/Reprogram Cycles
Cycles
Table 2- 0008B
3
Specifications
ispLSI 1024
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
≤
3ns 10% to 90%
1.5V
1.5V
See figure 2
Figure 2. Test Load
+ 5V
R1
Device
Output
R2
CL
*
Test
Point
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
Table 2- 0003
3-state levels are measured 0.5V from steady-state
active level.
Output Load Conditions (see figure 2)
Test Condition
A
R1
R2
CL
*
CL includes Test Fixture and Probe Capacitance.
470Ω
390Ω
390Ω
390Ω
35pF
35pF
35pF
5pF
B
Active High
∞
∞
Active Low
470Ω
C
Active High to Z
at
V
OH
- 0.5V
at
V
OL
+ 0.5V
390Ω
Active Low to Z
470Ω
390Ω
5pF
Table 2- 0004A
DC Electrical Characteristics
Over Recommended Operating Conditions
CONDITION
SYMBOL
PARAMETER
MIN.
–
–
–
–
–
–
–
–
TYP.
3
–
–
–
–
–
–
–
MAX.
0.4
–
UNITS
V
V
µA
µA
µA
µA
mA
mA
mA
V
OL
V
OH
I
IL
I
IH
I
IL-isp
I
IL-PU
I
OS
1
Output Low Voltage
I
OL
=8 mA
Output High Voltage
I
OH
=-4 mA
2.4
Input or I/O Low Leakage Current
isp Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
0V
≤
V
IN
≤
V
IL
(MAX.)
-10
10
Input or I/O High Leakage Current
3.5V
≤
V
IN
≤
V
CC
0V
≤
V
IN
≤
V
IL
0V
≤
V
IN
≤
V
IL
(MAX.)
-150
-150
-200
190
215
V
CC
= 5V, V
OUT
= 0.5V
I
CC
2,4
Operating Power Supply Current
V
IL
= 0.5V, V
IH
= 3.0V Commercial
130
135
f
TOGGLE
= 1 MHz
Industrial/Military
1. One output at a time for a maximum duration of one second. V
out
= 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.
2. Measured using six 16-bit counters.
3. Typical values are at V
CC
= 5V and T
A
= 25
o
C.
4. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the Power Consumption sec-
tion of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book and CD-ROM to estimate maximum
Table 2-0007A-24 w/mil
I
CC
.
4
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